DATE: 04-22-2011 HOTFIX VERSION: 029 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 789198 CAPTURE PROPERTY_EDITOR Newly added user property to a symbol can not be moved on the schematic page. 812501 CAPTURE NETLIST_OTHER Extension of PADS netlist is .NET in V16.3. It should be .ASC. 842161 CIS GEN_BOM CIS standard BOM taking long time 844125 CAPTURE NETLISTS Normal and convert view placed in same design don't get netlisted due to duplicate power pin names. 847688 CAPTURE PROPERTY_EDITOR Property Editor changes selection on Display 851044 CAPTURE GEN_BOM "Export BOM report to Excel" does not appear in the Standard Bill of Material Window. 862785 CAPTURE NETLISTS RINF netlist with net attributes generetaed by capture 16.3 is not getting loaded in CADSTAR tool 868118 CAPTURE NETLIST_ALLEGRO Differential pairs not getting netlisted in hierarchical design. 869630 ALLEGRO_EDITOR DATABASE Request - support additional dielectric layers above the top conductor layer for flex designs. 880219 CIS GEN_BOM Standard CIS BOM does not viewed properly if underscore presents in Part_Number property 881792 ALLEGRO_EDITOR SHAPE Cannot Delete the Islands on the shape. No Error reported. 882128 SPECCTRA HIGHSPEED Difference in length report between Allegro and SPECCTRA 883224 SIG_INTEGRITY SIMULATION crash while reflection simulation from Constraint Manager 883291 SIG_INTEGRITY OTHER Z-axis delay causes incorrect actual values for delay 883971 APD EDIT_ETCH APD crashed when I tried to add cline in (-6674.79 -7506.74) via. 884061 CAPTURE SCHEMATIC_EDITOR multi-line text zoom doesn't work correctly 884181 ADW DBEDITOR Parts get released anyway without any errors flagged. 885019 CAPTURE GEN_BOM Create BOM causes Capture crash with include file 886437 ALLEGRO_EDITOR SHAPE Change of behavior of NET_SHORT between 16.2 and 16.3 887190 ALLEGRO_EDITOR PADS_IN getting parse error during PADS to Allegro Import 887348 ALLEGRO_EDITOR MENTOR mbs2brd translator crashing without any error message in attached testcase -v16.3s027 DATE: 04-8-2011 HOTFIX VERSION: 028 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 704398 CONCEPT_HDL CORE In Windows mode basic shortcuts do not work when in German language 771137 ADW LRM LRM reports 'Injected Mismatch' for a value based on capitalization of ptf value 872547 CONCEPT_HDL CORE Document schematic - Published PDF is missing Bookmarks 875001 CONSTRAINT_MGR OTHER Click on the Constraint Manager selected net filter icons crash software. 875039 CONSTRAINT_MGR ANALYSIS RPD margin is not calculated in 16.3 876275 CONCEPT_HDL CONSTRAINT_MGR Constraint Manager not retaining target net 877912 APD DRC_CONSTRAINTS Shape to Shape DRC seems to be behaving inconsistenly above 90 um spacing on mcm database. 878022 CONCEPT_HDL CONSTRAINT_MGR NO_XNET_CONNECTION is not working unless defined on last discrete before receiver 878519 SIG_EXPLORER OTHER View Trace Parameter - stripline trace model display incorrect distance to the reference plane 879529 CAPTURE NETLISTS Misleading bus/pin ERROR [NET0081] message from PSpice netlist 881455 ALLEGRO_EDITOR INTERFACES Some Drill Figures missing while Exporting DXF 881711 ALLEGRO_EDITOR SCHEM_FTB Spacing constraints(Net Class) from schematic are not transferring correctly to the layout 882277 ALLEGRO_EDITOR DRC_CONSTR Get Bogus (false) "Thru Pin to shape spacing" DRC for Oval slotted pads. 882408 SCM SCHGEN Export physical fails due to netlisting error with the ASA exported schematic 882796 APD OTHER GDS stream import results in a set of bumps misplaced... possibly rotated 90 degrees DATE: 03-25-2011 HOTFIX VERSION: 027 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 820901 EMI SETUP Request EMC system.conf file that can be read from CDS_SITE. 861999 ALLEGRO_EDITOR DRC_CONSTR DRC hang after padeditdb 862463 CONCEPT_HDL RF_LAYOUT_DRIVEN Rotating and Mirroring RF components in DE-HDL requires RFFLIPMODE property to be correctly updated 867223 ALLEGRO_EDITOR SHAPE Shape fill disappears when Negative shape is converted to Positive in Cross Section 868733 CONCEPT_HDL ARCHIVER ASA Archiver not saving the entire design. 871548 ALLEGRO_EDITOR MENTOR Shapes missing after mbs2brd translation 872003 SIG_EXPLORER SIMULATION TDR simulation results were different between 15.7 and 16.3. 872464 CONCEPT_HDL CORE DEHDL script works in SPB16.2 but not in SPB16.3 873772 SCM CONSTRAINT_MGR Importing a block results in subblocks coming in without properties 874335 SPECCTRA ROUTE Route Custom crashes SPECCTRA after routing for some time during "Running Route Phase". 874989 CAPTURE SCHEMATICS Schematics jumps to another page after a mouse click 875161 CAPTURE NETLISTS Creating Allegro netlist hangs Capture 875411 ALLEGRO_EDITOR NC NC drill produces Error processing extract . Program terminated. 876004 ALLEGRO_EDITOR SHAPE Unused pad suppression problem in Allegro v16.3 since S020~S024 876045 ALLEGRO_EDITOR SHAPE Oval hole drills do not void shape with hole shape drc when the regular pad is smaller than hole 876168 SPECCTRA_MENT_ IMPORT option to have a switch to prevent merging of plane layers during mbs2sp 876210 ALLEGRO_EDITOR SHAPE When updating shapes to Smooth the tool will hang. 876284 ALLEGRO_EDITOR DATABASE Executing SKILL file crashes Allegro 877057 ALLEGRO_EDITOR MENTOR Footprints are shifted when importing from boardstation 877549 SIP_LAYOUT WIREBOND Wirebonds not moving correctly when on an Interposer smaller than the die. 877862 APD WIREBOND APD crashed when add Wirebond without any dump and cannot record script. 878199 CIS DERIVE_NEW_DB_PA Change in Regional Setting causing problem in derive database 878216 APD OTHER stream_in - Stream file scan failed 878400 APD WIREBOND unable to add a wire bonding on few die pad DATE: 03-11-2011 HOTFIX VERSION: 026 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 851882 SCM SCHGEN Multiple issues with the ASA generated schematic in preserve mode while using square bracket 852063 ALLEGRO_EDITOR EDIT_ETCH What is being displayed in the HUD when a percentage is specified as a tolerance? 854502 ALLEGRO_EDITOR DRC_CONSTR DRC not detected until DBDoctor is executed. Status form and sum dwg report are incorrect. 856797 EMI RULE_CHECK Arc segments were detected as warning by bypass_plane_split. 859213 PCB_LIBRARIAN CORE $LOCATION size in PDV and DEHDL differ 860772 ADW PCBCACHE Save Shopping Cart (pcbcache) is crashing component browser 862259 SIG_INTEGRITY FIELD_SOLVERS EMS2D run twice during View Topology. 865158 ALLEGRO_EDITOR SHAPE Shapes are not voided with Dynamic Shape Fill modes with Regions 865295 PCB_LIBRARIAN CORE Part Developer crashs with symbols having Japanese notes 866095 PCB_LIBRARIAN EXPORT_OTHER Export DE HDL part to Capture Part Crashed 866835 SCM UI User arguments not used over project arguments for new tool 867102 CAPTURE LIBRARY Incorrect pin number gets assigned to pin if a PDF is opened before writng the pin number. 868092 CAPTURE GEN_BOM Capture BOM in V16.3 is different than that of V16.2 for attached test case. 868517 ALLEGRO_EDITOR ARTWORK A pinhole was made in the artwork file. 868646 ALLEGRO_EDITOR SCHEM_FTB Change in the PIN_GROUP at the chips level not propagated to the board file does not allow the swap 868844 PCB_LIBRARIAN CORE BUBBLE_GROUP with no value causes problematic symbol 869326 CIS DESIGN_VARIANT View Variant is not showing part as Do Not Stuff 869547 ALLEGRO_EDITOR SCHEM_FTB Error while parsing the alternate symbol 869931 SIG_INTEGRITY OTHER DML Library Management rewrites library longer then 512 characters into multiple lines. 869960 F2B PACKAGERXL PART_NAME property added to Export Packageable schematic parts 870392 APD EDIT_ETCH Route > Slide not performing as expected in 16.3 870704 ALLEGRO_EDITOR PARTITION 2nd import of parttiotion unplace components in master 871177 CAPTURE LIBRARY Keyboard shortcut for closing the Place Part window 871552 PSPICE SIMULATOR Pspice tool crash 871643 ALLEGRO_EDITOR INTERFACES IDF in batch and GUI for dra files fails to calculate extents correctly 871968 ALLEGRO_EDITOR COLOR After using Clear All Nets, Color Dialog box needs to be reopened for adding custom colors. 872352 APD WIREBOND Move Guide paths crashed APD. 872380 CONCEPT_HDL COMP_BROWSER DEHDL crash when editing the ppt_optionset.dat file from Part Manager. 872450 APD WIREBOND Wire to die edge angle remains highlighted in red for wire bond status window in v16.3 872787 APD WIREBOND Some Unused Wire profiles be purged but still existing in Bond Wire Profile of Color Visibility? 873217 ALLEGRO_EDITOR TESTPREP Testpoint generation not working correctly 873500 APD REPORTS Total Plating value is 0 873505 APD MANUFACTURING fillet size changed when recreate Plating Bar 873600 APD OTHER When attempting to Display Pin Names the tool takes a very long time. 874341 ALLEGRO_EDITOR OTHER "Gloss>Convert corner to arc" command made an unnecessary circular arc. DATE: 02-26-2011 HOTFIX VERSION: 025 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 746063 CIS OTHER CIS Query Does not display initial search results 779588 ALLEGRO_EDITOR PLACEMENT Symbol outline not rotated with component. 805616 ALLEGRO_EDITOR ARTWORK Allegro produces warning about database extents exceed film size 843145 CONCEPT_HDL CORE Cannot copy grayed out properties in the Attributes form to the buffer 845607 ALLEGRO_EDITOR EDIT_ETCH Sliding with arc gridless enabled leaves extra segments behind and 45 degree segment. 850428 SIG_EXPLORER SIMULATION SigXP failed to simulate the topology with designlink. 853665 SPECCTRA CHECK Scheduling violations reported incorrectly. 855534 CONSTRAINT_MGR OTHER formula result does not update when length changed 855793 CONCEPT_HDL CORE Rename Pin on Block is not working in DE HDL with HF 21 856306 ALLEGRO_EDITOR INTERACTIV Modifying pad instance corrupts db 859437 SIG_INTEGRITY GUI Log Scale setting of EMS2D was cleared by re-open design. 859850 SIG_INTEGRITY GEOMETRY_EXTRACT Allegro freeze during topology extraction with EMS2D. 860366 CAPTURE CONNECTIVITY Netlist is different in V16.3 than in V16.2 860809 F2B BOM Bomhdl failed to create the design view check for existance of the packaged directory 861027 CONSTRAINT_MGR CONCEPT_HDL Unable to synchronize the constraints 862137 SIP_LAYOUT OTHER SPB 16.3 SiP Logic - Derive assignment is unable to resolve connectivity of shapes 862980 ALLEGRO_EDITOR EDIT_ETCH When sliding a via the potential DRC behaviour is inconsistent. 863400 SPIF OTHER SPIF does not translate the oblong pads correctly 864363 APD REPORTS The Wirebond report is failing because there are Non-standard Bond wires present. 864621 ALLEGRO_EDITOR DATABASE Database corrupted after adding layers in Cross Section and trying to save the board file. 865875 ALLEGRO_EDITOR MENTOR mbs2brd translator results in broken/unrouted nets even though the BoardStation design is fully routed 866202 CONSTRAINT_MGR OTHER Worksheet File import fails with error message due to character limit 866726 CONCEPT_HDL CREFER TOC (table of content) not generated in schcref_1 schematic (CREFER flattened output). 867238 CONSTRAINT_MGR INTERACTIV Split Xnet for diff pair crashes PCB editor 867696 SIP_LAYOUT DIE_STACK_EDITOR When doing an Info on this design it will crash. 867742 ALLEGRO_EDITOR DATABASE Thermal Pad view for shapefillet on Negative layer 867842 CAPTURE PROJECT_MANAGER Capture crash with 'Open File Location" 868306 CAPTURE CONNECTIVITY mirror vertically removes junction creates extra nets 869758 CAPTURE GENERATE_PART Generate Part option "Copy schematic to library" does not copy schematic page attributes 869941 ALLEGRO_EDITOR PADS_IN PADS_IN unable to import Power PCB 2005.0 file in 16.3 but works with 16.2 870301 SIP_LAYOUT SHOW_ELEM When selecting Info and then a rectangle shape, the tool will crash. DATE: 02-11-2011 HOTFIX VERSION: 024 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 858051 ALLEGRO_EDITOR OTHER Allegro's Help>About... System Info... doesn't work on Win7 862703 ALLEGRO_EDITOR DATABASE crash when doing a save_as 866288 ALLEGRO_EDITOR NC Drill customization table won’t let you add characters in lower case 866310 ALLEGRO_EDITOR DRC_CONSTR Testprep doesn't create a DRC for Testpoint > Component 866652 ALLEGRO_EDITOR SCHEM_FTB Allegro Spacing net class not updated with new logic DATE: 01-28-2011 HOTFIX VERSION: 023 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 739067 SIG_INTEGRITY SIMULATION about modal delay of diff pair net 742237 CIS FOOTPRINT_VIEW 3D Footprint view in CIS Explorer 762702 CONCEPT_HDL CORE Unable to change color settings 800333 CONCEPT_HDL CORE Text change cursor not working on Solaris and Linux 837479 CONSTRAINT_MGR DATABASE Import dcf with custom column cuases a problem 846679 ALLEGRO_EDITOR SHAPE Through Pin can not be voided correctly in dynamic shape. 852255 CONCEPT_HDL COMP_BROWSER DEHDL crashes when adding part from cat file 855553 ALLEGRO_EDITOR DRC_CONSTR Multithreaded DRC shows different DRC counts 856459 SIG_INTEGRITY GEOMETRY_EXTRACT No waveform was output if users set the Via type to Analytical type 857030 SIG_INTEGRITY OTHER Inconsistency when signal model has "legal" spaces within it. 857120 APD WIREBOND Enhancement for Redistribute Fingers. 857165 SIG_INTEGRITY OTHER Model Name Changed Warning appears every time after Export Physical 857237 ALLEGRO_EDITOR SCHEM_FTB UserDefined mapping mode 857650 ALLEGRO_EDITOR DRC_CONSTR Hole to line DRC unavailable on inner layers for mechanical pin with no regular pad definition. 858046 MODEL_INTEGRIT TRANSLATION Ibis2signoise fails translation when the unit of Pin section is "ohms". 858154 GRE DETAIL Net not following the plan during Plan Topological 858192 SIP_LAYOUT SHAPE Program crashes when attempting to add polygon shape. 858307 CIS DESIGN_VARIANT Homogenous part not showing correct DNI on schematic 858624 ALLEGRO_EDITOR PAD_EDITOR "Save Padstack to 16.2" command is needed in 16.3 pad_designer. 858814 ALLEGRO_EDITOR MODULES place module not placing figures present in mdd 859514 APD IMPORT_DATA Die Text-in cannot change unnamed Begin Layer to selected pad layer in step 4 859640 ALLEGRO_EDITOR PLOTTING Shape based pads not output as polygon in IPF 859680 ALLEGRO_EDITOR DRC_CONSTR Multithreaded DRC shows different DRC counts 860069 ALLEGRO_EDITOR OTHER Import Logic hangs then crashes and displays Netrev warnings. 860535 APD DXF_IF a2dxf got an error message 860860 CONCEPT_HDL COMP_BROWSER Component Browser freezes 861295 CONSTRAINT_MGR ECS_APPLY Diff pair PCSet value overrides ECSet values in constraint manager spreadsheet. 862279 SPIF OTHER running 'Allegro PCB Router' Crashes DATE: 01-14-2011 HOTFIX VERSION: 022 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 372240 CAPTURE SCHEMATIC_EDITOR Allow component move with connectivity change should be checked by default 769139 SIP_LAYOUT DRC_CONSTRAINTS Wire to Bond finger rule in the CM needs profile to profile constraint capability 772299 ALLEGRO_EDITOR GRAPHICS Via doesn't get highlighted properly with OpenGL disabled 830519 ALLEGRO_EDITOR GRAPHICS Disabling openGL causes highlihting problems. 833981 RF_PCB FE_IFF_IMPORT DE HDL Import IFF unit conversion and unit display in RF schematic 835698 RF_PCB FE_IFF_IMPORT DE HDL Import IFF to assign simple sig_names like RF001 RF002 etc 840094 RF_PCB OTHER dlibx2iff does not translate complex polygon pad 844504 SIG_EXPLORER INTERACTIV EMI Regulation setting of the board is not reflected correctly when the net is extracted into SigXP 846210 PDN_ANALYSIS PCB_STATICIRDROP IR Drop mesh is not correct. 846228 SIG_INTEGRITY OTHER ZAll and Wirebond calculation in the Prop Delay formula 846259 CONSTRAINT_MGR CONCEPT_HDL Why dont I see the P1_8V_DIG net in CM ? 847278 CAPTURE TCL_INTERFACE TCL/TK PDF Export Change Page Size 847942 SIG_EXPLORER OTHER The solder resist layer was not included in Interconnect Model of SigXP. 848181 PSPICE DEHDL Model association for concept symbols with a chips view doesnt work 849707 ALLEGRO_EDITOR MANUFACT Thieving creates unwanted thermal reliefs in this design. 851070 CONSTRAINT_MGR CONCEPT_HDL The Match Groups are not visible in the CM 851171 F2B PACKAGERXL Design will not package with exclude_cdsNotOnSym 851290 APD PADSTACK_EDITOR APD/SiP crashes when the user defined mask layer is edited with padeditdb. 851477 SPECCTRA ROUTE Allegro Router runs out of memory during route passes 851658 APD EDIT_ETCH bunceback behavior while slideing cline 851725 ALLEGRO_EDITOR DATABASE Number of DRC is not consistent on each DRC update. 851789 ALLEGRO_EDITOR SKILL Skill axlAirGap for Via & Text causes Allegro to crash 852325 ALLEGRO_EDITOR DATABASE Perf advisor doesn't check high pincount devices for RATSNEST_SCHEDULE 852360 SIG_INTEGRITY OTHER Appling toplogy template to a diff pair object reports UserDefined in CM 852395 ALLEGRO_EDITOR DRC_CONSTR Same net via spacing broken drc shows up to date 852764 ALLEGRO_EDITOR SKILL axlHttp beeps and gives error E - http 42 852787 CAPTURE ANNOTATE Tool is crashing during annotation if Ref Control is set 853110 ALLEGRO_EDITOR ARTWORK Allegro Crash on selecting Mfg > Artwork if any Parameter syntax is wrong in art_param.txt 854031 ALLEGRO_EDITOR MANUFACT The stream out data xxx.scf seems to be incorrect. 854246 ALLEGRO_EDITOR MANUFACT Stream out data of Oblong pad is strange. 854293 APD OTHER dynamic fillets were disappeared when open in 16.3. 854356 ALLEGRO_EDITOR OTHER Fillet adding doesn’t check same net spacing rule in both static and dynamic mode. 855101 ALLEGRO_EDITOR OTHER Drill figures now smaller than expected 855124 APD PLOTTING The "load plot" command did not import Drill symbols(Figure) and Characters in APD. 855348 ALLEGRO_EDITOR EDIT_ETCH Differential Pairs do not slide to correct geometry 856220 ALLEGRO_EDITOR INTERFACES Export DXF in the 16.3 S021 build rotates some pin locations 856256 SIP_LAYOUT WIREBOND When editing a single Wirebond all wirebonds attached to the finger get highlighted. 856674 ALLEGRO_EDITOR AUTOVOID drill hole to shape autovoiding clearence is wrong for Same Net Spacing DATE: 12-10-2010 HOTFIX VERSION: 021 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 708992 ALLEGRO_EDITOR SCHEM_FTB Design Differences fails with Error #534 748982 CIS FOOTPRINT_VIEW Respective pin number from schematic does not get highlighted on 3-D footprint viewer. 775788 CONCEPT_HDL COMP_BROWSER Component Browser search is too slow 802152 PCB_LIBRARIAN IMPORT_EXPORT cap2cond design translator is also looking for Capture feature string in license - this is break from 16.2 803910 ALLEGRO_EDITOR GRAPHICS Request Rat like display for REFDES text to component. 823599 SCM REPORTS Ability to generate DEHDL style BOM report 826558 CONCEPT_HDL LWB-HDL Module definitions for cells is not included in the simulation verilog netlsit on LINUX 828689 CONSTRAINT_MGR OTHER formula constraint lost when Constraint Manager closed 831192 SIG_INTEGRITY GUI Cannot close Analysis Preferences window. 831229 ALLEGRO_EDITOR INTERACTIV When mirroring sym PLACE_BOUND shape does not mirror til placed 832315 ALLEGRO_EDITOR SCHEM_FTB ECO.txt file should not list net names if schematic and board files are synchronized. 832644 ALLEGRO_EDITOR DRC_CONSTR DRC error disappears when the size of Constraint region is changed. 833061 MODEL_INTEGRIT TRANSLATION Model Integrity IBIS2DML fails to convert data correctly for pre-emphasis using Driver Schedule 833487 SIG_INTEGRITY GEOMETRY_EXTRACT Probe sim failed if VARIANT_TO_IGNORE was set. 833922 CONCEPT_HDL CORE Move pin on blocksymbol using Block -> Move Pin command change the Pinname textsize 834103 ALLEGRO_EDITOR DRC_CONSTR dynamic diff phase highlight not showing 834868 SIG_EXPLORER OTHER View Trace Param crash if sweep param was set for loss tangent. 835006 CONCEPT_HDL OTHER Locked BACKGROUND directive is changed in DEHDL session 835326 APD SPECCTRA_IF Specctra does not open from APD using Allegro Package Designer XL (Legacy) license 835622 CONCEPT_HDL CORE DE-HDL crashes when selecting wire having global sig_name in opened block schematic 836962 CONSTRAINT_MGR ANALYSIS Simulation will crash 837216 CONSTRAINT_MGR OTHER Custom measurement Rslt lines being duplicated in a different worksheet. 837322 CAPTURE LIBRARY Library is not getting freed even when user has closed it. 839517 CAPTURE MACRO Macros (for place part) created on 16.2 version works differently on 16.3 839749 ALLEGRO_EDITOR MANUFACT Drill entries are repeated in .drl files 840738 ALLEGRO_EDITOR ARTWORK Shape symbol in padstack moves when Artwork is generated - Break again after fix in 16.0 841176 CAPTURE ANNOTATE Homogenous parts are not getting packaged correctly in annotation in 16.3 841355 SIG_EXPLORER OTHER Trace model parameter does not update when linear Range are entered. 841730 CONSTRAINT_MGR OTHER Allegro Crashes while working with MGs in CM 841759 F2B BOM BOM creates an incomplete output when design packages without errors 841928 CONCEPT_HDL CHECKPLUS CheckPlus fails when pin name contains _N in the middle of the pin name 841991 ALLEGRO_EDITOR PLOTTING Offset of text and line on importing a plt file 842204 ALLEGRO_EDITOR DRC_CONSTR Arc creates false DRC on edge of Constraint Area 843114 SPECCTRA ROUTE Specctra rules file taking very long time to load 843254 CONCEPT_HDL CONSTRAINT_MGR Unable to invoke CM from DEHDL CM Crashes with an error Olecs.exe The application has quite unexpectedly 843518 F2B DESIGNVARI Variant with FAIL_OPEN 843933 ALLEGRO_EDITOR DRC_CONSTR Cancelling drcupdate will either hang or crash Allegro 844074 APD SPECCTRA_IF Export Router fails with memory errors. 844246 ALLEGRO_EDITOR SHAPE Long Thermal_Relief connecting to XHatch shape 844355 CONCEPT_HDL COMP_BROWSER User seeing CDS_NA appear when placing component 844381 ALLEGRO_EDITOR SCHEM_FTB 3rd party netin - Pin is connected to net not reconnected. 844662 SIG_INTEGRITY OTHER Cannot uncheck options in analysis preferences. 844796 SIG_INTEGRITY OTHER Get an error E- Illegal model name. Cannot add model RE_RES_0402-16570580,when doing Auto Setup during Model assignment 846172 APD OTHER Cannot generate the dxf file from this database 846270 SPECCTRA GUI SIGNAL_15 layer missing from the color pallete in Specctra 846352 ALLEGRO_EDITOR DRC_CONSTR Route connect does not select the pin-pair width for routing. 846420 F2B DESIGNSYNC Design Sync failes due to FUNC_VIEW_FILE missing messages 846918 ALLEGRO_EDITOR PADS_IN Pads_in crashes when importing ASCII file, Runtime Error 847079 ALLEGRO_EDITOR DATABASE Allegro Crash while trying to unlock the board file 848143 F2B DDBPI Adding part crashes DEHDL 848415 CAPTURE STABILITY Crash on Mirror Horizontally DATE: 11-11-2010 HOTFIX VERSION: 020 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 501606 CAPTURE OTHER Descend Hierachy does not open first page 764482 SPECCTRA CHECK Allegro router same net checking different then PCB Editor. 809055 APD EDIT_ETCH Shove Preferred changes trace widths of shoved traces during routing 816920 ALLEGRO_EDITOR PLACEMENT Update symbols causing Allegro to crash 826762 SIG_EXPLORER OTHER The rotation of element are different between pre 16.2 and 16.3. 827769 CIS FOOTPRINT_VIEW 3D footrpint viewer doesn't shows circular geometry on footprints 828830 F2B DDBPI LRM does not update Parts which have a ALT_SYMBOLS value Added 830319 SIG_INTEGRITY SIGWAVE Sigwave load errors out with "Requested resource was not available" after large bus simulation 830359 CAPTURE GENERAL Crash on link Database Part 830627 ALLEGRO_EDITOR DRC_CONSTR Incorrect thru pin to shape SPACING error 830716 CAPTURE PRINT/PLOT/OUTPU Capture crashes while printing a Capture CIS Standard BoM with ISR s0017. 830791 SIP_LAYOUT LEFDEF_IF Improve the LEF Library Manager to import passivation layers 831210 CAPTURE OTHER Users get an error message everytime While running Update Cache with V16.3 and V16.2 with latest ISR 831231 PSPICE SCHEMATICS pspice com wrapper error 831692 ALLEGRO_EDITOR PLACEMENT Application becomes sluggish to nonresponsive when trying to place mechanical symbol 831704 CONCEPT_HDL CORE ASA stuck in an error condition. 833116 PCB_LIBRARIAN IMPORT_EXPORT Getting LMF-02018 Error while Importing Capture Parts 833433 ALLEGRO_EDITOR TECHFILE techfile in/out round-off a value of Conductivity(Xsection). 833921 ALLEGRO_EDITOR ARTWORK Gerber filled lines stick out from filled area on Fillets 833950 ALLEGRO_EDITOR ARTWORK Artwork process create recrementitious circle for AutoSilk data. 833975 SIP_LAYOUT DATABASE pad not on subclass 834152 APD EDIT_ETCH Route Slide of a Diff_pair section moves all of the cline instead of just the segment that you want. 834861 APD OTHER package integrity runs for hours. results in no more room in database 835367 CONCEPT_HDL SECTION Packager-XL reverses the pin numbers of connectors 837805 ALLEGRO_EDITOR EDIT_ETCH Add Connect crashes Allegro when routing from a cline (not on a net) through a region. 838057 CONCEPT_HDL CHECKPLUS CheckPlus crashes with long parameter. 838356 SPIF OTHER File > Export > Router Crashes Allegro and dsn file creation stops 838521 APD MANUFACTURING When creating pbar some clines are gone. 838766 ALLEGRO_EDITOR EDIT_ETCH Sliding with arcs making sharp corners instead of arcs. 838830 SIP_LAYOUT ASSY_RULE_CHECK Assembly rule check flagging a DRC for item not near edge border 838836 ALLEGRO_EDITOR SKILL Pb to check license with skill core function 839218 APD 3D_VIEWER 3D view of this mcm file is not getting rendered and the 3D GUI screen shows up blank in APD 839362 ALLEGRO_EDITOR EDIT_ETCH trying to slide a bbVia crashes Allegro 839984 ALLEGRO_EDITOR ARTWORK Some pinholes were made in the artwork file. 840016 CONSTRAINT_MGR INTERACTIV Cannot manually create pin pair for unspec pins of Xnet. 840455 ALLEGRO_EDITOR INTERFACES IDF exported/imported from symbol have no drill information for pad. 841431 CAPTURE NETLIST_ALLEGRO Upgrading from Capture V16.2 to V16.3 some nets get shorted on the schematic page. DATE: 10-20-2010 HOTFIX VERSION: 019 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 717365 SCM SCHGEN Option for Schematic Block to have the defined Sheet symbol/Page Border 751477 ADW COMPONENT_BROWSE UCB in DB mode does not read local worklib for block symbols 792545 APD PADSTACK_EDITOR Can not rename user defined Mask Layer in APD/SiP. 813436 SCM OTHER Option to have a directive in the cpm file to distinguish an SCM project from a DE HDL Project 820640 SIG_EXPLORER OTHER SigXP Crash after doing Transform For Constraint Manager 824527 CAPTURE PRINT/PLOT/OUTPU Part ref-des resets when trying to take variant print from Part Manager 824688 SIG_INTEGRITY GEOMETRY_EXTRACT PCB-SI crashes when running more than 2 simulations 826571 CONSTRAINT_MGR OTHER Import of .dcf crashes in 16.2 but not 16.3 826626 CONSTRAINT_MGR OTHER Creating a Netclass from a custom worksheet breaks the Netclass object upon the next invocation of Constraint Manager. 826799 SIG_EXPLORER SETUP_ADV can not close Analysis Preferences form when Advanced Setting button is opened and closed once 827375 ALLEGRO_EDITOR DATABASE Need to check why Net class assigned on the Net are not visible in CM 827521 CONSTRAINT_MGR OTHER Allegro crashes when trying to open Constraint Manager. 827713 SIG_EXPLORER INTERACTIV Cannot move object by click and drag after RMB>Note. 828803 CIS UPDATE_PART_STAT Crash on update part status from Part Manager 829005 SIG_INTEGRITY FIELD_SOLVERS SigXP crash when RMB click on the Trace Model with EMS2D. 829008 SIG_INTEGRITY FIELD_SOLVERS SigXP crash when RMB click on the Trace Model with BEM2D. 829233 CONSTRAINT_MGR UI_FORMS Physical Csets applied on a diffpair is not followed while routing, though visible in CM. 829340 CAPTURE LIBRARY_EDITOR propertries are shifting after being placed 829747 SIP_LAYOUT DIE_EDITOR Move pin incremental coordinate 829991 SIP_LAYOUT OTHER The "axlAddAutoAssignNetAlgorithm" function is missing from the Allegro SKILL documentation. 830509 APD ARTWORK The measured airgap aren't between features in the design aren't consistent in Import > Artwork. 830809 ALLEGRO_EDITOR TESTPREP In the testprep report the Pin type is getting appended with net name 830907 SIP_LAYOUT DIE_GENERATOR SiP will crash when adding a Standard DIE using the Die Generator. 831176 ALLEGRO_EDITOR MANUFACT Testprep Resequence crashes this design. 831199 SIG_EXPLORER OTHER error in _sxUtilGetAllegroPart message was displayed. 831610 ALLEGRO_EDITOR EDIT_ETCH Sliding with Diagonal Entry (45 Degree) is sliding the the adjacent vertical segment when Constraint region is present 831946 ALLEGRO_EDITOR OTHER Cannot re-open Command Browser if it was closed by Undo. 831998 ALLEGRO_EDITOR SHAPE Allegro crash when user execute shape vertex add command. 832059 APD SHAPE Shape does not keep Shape-Via(w/ Fillet) spacing. 832169 ALLEGRO_EDITOR EDIT_ETCH Sliding with Diagonal Entry (45 Degree) is sliding the the adjacent vertical segment when Constraint region is present 832197 ALLEGRO_EDITOR EDIT_ETCH Sliding diffpair slides adjacent segment 832613 ALLEGRO_EDITOR EDIT_ETCH Adding microvia and bbvia crashes allegro at location where overlapping shapes exist on other layer 832922 ALLEGRO_EDITOR PARTITION Import partition board crashes Allegro. 833127 ALLEGRO_EDITOR SYMBOL With 'unused pads suppression' the padstack (clearance) does not get rotated in the internal layer 833251 ALLEGRO_EDITOR SCHEM_FTB Power planes on Layer E3 and E18 change to dummy net after Refresh Module. 833586 ALLEGRO_EDITOR PLACEMENT Allegro crashes while placing jumper DATE: 10-7-2010 HOTFIX VERSION: 018 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 398114 ALLEGRO_EDITOR INTERACTIV Need to differentiate between tracks and shapes on an etch layer. 530659 ALLEGRO_EDITOR UI_FORMS Allegro Place Manually and Update Symbols GUI missing checkboxes on Windows Vista 770576 ALLEGRO_EDITOR INTERACTIV Design Partition - Place replication not working correctly 777925 CAPTURE OTHER Capture crash immediately after invoking 807089 FLOORPLANNER INTERACTIV Logic > Net Logic hangs tool in Linux 809118 CAPTURE NETLISTS ENH to compare two schematic Capture designs 812046 CAPTURE NETLIST_ALLEGRO Design not getting netlisted in V16.3 due to illegal characters in pin nmaes 814607 SIP_LAYOUT IO_PLANNER update genfeed to add options to dumbp all chips files from design 814750 ALLEGRO_EDITOR DRC_CONSTR BBvia and Microvia overlap DRC issue 815621 SCM OTHER Enhance time shown in session log to support DST 815681 CONCEPT_HDL CORE The TOC symbol shows multiple entries for the pages 817380 ALLEGRO_EDITOR DRC_CONSTR Incorrect or bogus line to line DRC errors are appearing between the nets of a diffpair 817881 APD ETCH_BACK Create Etch Back Mask failed 820771 ALLEGRO_EDITOR PLOTTING axlLayerPrioritySet does not provide the same capability than the 15.7 Color Priority system 820773 ALLEGRO_EDITOR INTERFACES Import 3rd Party Logic $SCHEDULE removes visible ratsnest from database when using T-Points 820792 ALLEGRO_EDITOR INTERFACES Import $Schedule command is returning illegal loop error for pin-pair based rules 821133 ALLEGRO_EDITOR MANUFACT Output artwork for pad data that are suppressed unconnected pads with Gerber 6x00 format 821504 MODEL_INTEGRIT TRANSLATION dmlcheck failed when .dml translated from .mod was opened by MI. 821827 ALLEGRO_EDITOR EDIT_ETCH Allegro Crash on routing Diff Pairs 821836 CONSTRAINT_MGR OTHER Why the min/max propagation delay analysis is failing for one of the pin pair in this design! 822090 CONCEPT_HDL CONSTRAINT_MGR Crashed the Constriant Manager and SigXplorer from DE HDL 822744 CONSTRAINT_MGR DATABASE Xnet lost after DCF file imported into Constraint Manager 822827 PSPICE SIMULATOR Simsrvr crash upon running simulation 822844 ALLEGRO_EDITOR SCHEM_FTB Constraints are not updated in the brd file when working with Library defined diff pairs 822942 F2B DESIGNVARI Variant view does not show DNI on functions 823177 SCM BROWSER PPT_OPTIONSET_PATH defined using environment variable is not recognized by ASA 823200 ALLEGRO_EDITOR OTHER Import Logic hangs when dynamic phase control set 823589 CONCEPT_HDL CORE The operation could not be performed because no object on the drawing was selected 823821 ALLEGRO_EDITOR MANUFACT Allegro crash when trying to Gloss - 823833 CONCEPT_HDL CORE show vectors command 824902 ALLEGRO_EDITOR DATABASE Lose connectivity when copied via and cline structure 825289 ALLEGRO_EDITOR DRC_CONSTR duplicated drc and waive drc 825969 CAPTURE SCHEMATIC_EDITOR Refdes are getting reset after doing a replace cache/update cache for a generated pat 826068 ALLEGRO_EDITOR MANUFACT Adding Thieving on the negative plane layer doesn't show up 826266 ALLEGRO_EDITOR DRAFTING Datum Dimensioning Crashing Allegro in Linux 827032 SIP_LAYOUT ASSY_RULE_CHECK SiP Layout crashes when running Assembly Rules checks 827494 CAPTURE GEN_BOM Include file is overwritten for the STD Capture BOM if .txt file used as include file 827575 CONCEPT_HDL CONSTRAINT_MGR PINUSE 827708 APD 3D_VIEWER 3D viewer assign black color for all layer 828263 APD DXF_IF When the DXF out is executed, offset of the padstack is not correct. 828788 ALLEGRO_EDITOR DRC_CONSTR Soldermask Waived DRCs reappear in 16.3 829046 APD MANUFACTURING create plating bar makes net name changed to dummy net 829331 SIP_LAYOUT PLATING_BAR Create Plating Bar is deleting existing fillets. 829336 APD OTHER Request the ability to merge two nets together into a new net. DATE: 09-23-2010 HOTFIX VERSION: 017 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 676210 CAPTURE PRINT/PLOT/OUTPU Enhancement for correlate lower level pages with H blockes in PDF 736942 ALLEGRO_EDITOR INTERACTIV Autosave is not working with every application mode. 746256 CAPTURE ANNOTATE Intersheet refernces change their position in V16.3 even on unchecking ‘reset position’. 785417 CONCEPT_HDL COPY_PROJECT copyprojectui crashes with a Windows runtime error 791549 PSPICE PROBE PSpice cursor does not remember value outside zoom area 802639 F2B DESIGNSYNC BOMHDL crashes if colon is used as a sub design suffix separator 804475 CONCEPT_HDL OTHER RMB+MMW doesn't zoom in/out anymore with ISR012 807025 PSPICE PROBE Loading dat file slower in 16.3 as compared to 16.2 808550 CONCEPT_HDL OTHER On Linux Import design does not obey umask or setgid settings 810568 ALLEGRO_EDITOR PADS_IN Can PowerPCB 9.2 - Basic file be converted to Allegro? 812089 CONCEPT_HDL OTHER The colors on the Options form dont seem to match the colors displayed on the schematic canvas 812475 ALLEGRO_EDITOR INTERACTIV Saving .mdd always results in working directory 812836 CONSTRAINT_MGR DATABASE CM Custom Fomula -Handling of Pin_Delay is inconsistent in Analyze 812994 SPECCTRA ROUTE Max_total_vias constraint not working correctly when wiring option is set to "starburst". 816561 CONCEPT_HDL CONSTRAINT_MGR OLECS.exe Runtime Error occures when attempting to launch SigXP from a net in CM 816879 SIG_INTEGRITY SIGNOISE Program has encountered a problem and must exit in 16.3 S014(v16-3-85AT). 817006 SCM UI SCM copy signal changes existing signal names 817896 APD ETCH_BACK Etch back - improper use model 818242 ALLEGRO_EDITOR SHAPE Thermal relief connections not orthoganal and creating acute angles. 818429 ALLEGRO_EDITOR PLOTTING Pins created from shapes do not plot solid. 818513 F2B BOM Alphanumeric BOM not placing REF DES in proper order 818818 ALLEGRO_EDITOR INTERACTIV Place replication does not recognize mixed case characters in file path 818910 CAPTURE FPGA NC simulation flow is not working with 16.3 release 819108 SIP_LAYOUT DATABASE Wirebond profile constraints lost after saving and re-open sip 819151 SIP_LAYOUT ASSY_RULE_CHECK ADRC is showing X-D DRC markers on good Soldermask Shapes when doing a min. shape check. 819183 ALLEGRO_EDITOR MANUFACT NC Drill file generated for Backdrill layers show wrong Quantity of the drills 819269 SPIF OTHER File > Export > Router Crashes Allegro and dsn file creation stops 819463 ALLEGRO_EDITOR DATABASE VIA has illegal connections. 819842 ALLEGRO_EDITOR INTERFACES File Import Logic fails on syntax check when following documentation for $schedule command 820177 CONSTRAINT_MGR CONCEPT_HDL Net_class objects that are changed in CM at Front End are missing after Import Logic 820231 ALLEGRO_EDITOR DRC_CONSTR Allegro hangs when multi thread DRC is performed after updating padstacks 820373 SIP_LAYOUT OTHER Update symbol flags the "edited pins" error but still updates the symbol and then crashes. 820381 SIP_LAYOUT WIREBOND When opening a new design, with a design already open, the tool will use the first designs profile settiings 820634 CONSTRAINT_MGR OTHER Netrev fails without any useful message when importing ECO netlist 820665 ALLEGRO_EDITOR REFRESH Qvupdate is not working in 16.3 820849 ALLEGRO_EDITOR MANUFACT NC Drill has wrong quantity and also a drill is missing 821154 CONSTRAINT_MGR CONCEPT_HDL DE-HDL CM Import Analysis Results fails without any feedback 821195 CAPTURE OTHER Updating Cache generates errors including CAP0027 on Capture DE CIS with ISR s0014 and onwards. 821856 APD MANUFACTURING Create Bond finger Solder Mask issue 821936 SIP_LAYOUT COLOR Can not clear custom color of bondwire profiles 822841 ALLEGRO_EDITOR ARTWORK An issue about Gerber6X00 822842 SIG_INTEGRITY OTHER CM and Show element report different lengths 823559 SIP_LAYOUT BGA_EDITOR When doing an Edit > BGA the tool will shift the BGA's position when at 90 or 270 rotation. 823688 SCM SCHGEN Schgen changing the physicals bus name in the preserve mode for some of the bus 823792 CIS OTHER Capture CIS performance over WAN for bulk operations are slow DATE: 09-10-2010 HOTFIX VERSION: 016 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 604662 VLS-L VIA When changing Rows/Columns values in Edit Via Properties form, different value are assigned. 747191 PSPICE AA_SENS Pspice crashes when starting Advance Analysis 756103 CONCEPT_HDL ARCHIVER Archiver does not include all the Parts when design blocks are copied from one location to another 758487 APD 3D_VIEWER package substrate (BGA) outline should be on a separate layer, not on bottom conductor layer. 764417 APD EDIT_ETCH Routing with Diagonal entry (45 degree) to Constraint Regions does not work 766409 PSPICE PROBE Copy to Clipboard changes the label text colors 784577 CONCEPT_HDL COMP_BROWSER SingleclickAdd 'true' places does not pick the correct version 784814 SIP_LAYOUT ASSY_RULE_CHECK accuracy of acute angle DRC 792039 CONSTRAINT_MGR OTHER Doing a File->Import->Worksheet Customization from Constraint Manager will change the working directory. 796517 CONCEPT_HDL COMP_BROWSER Component Browser showing wrong symbol 801944 SCM UI SCM dropping terminators and pull-ups when renaming signals (copy - paste special) 804627 PSPICE PROBE Printet text labels have wrong location 810479 FSP DESIGN_SETTINGS Not able to connect some peripheral signals to FPGA manually 810814 CONSTRAINT_MGR OTHER T-point does not create when import DCF file. 811032 ALLEGRO_EDITOR EDIT_ETCH Enable enhanced pad entry to support pads as shapes 812643 SIP_FLOW CONSTRAINT_MGR Physical Constraint values disappear after entering constraint mode 812835 CONSTRAINT_MGR INTERACTIV CM Custom Fomula - "Analyze" on the header of Actual does not analyze pinpairs 813435 SIP_LAYOUT DIE_ABSTRACT_IF Invalid parameter passed to ICP utility API 814060 CONCEPT_HDL CORE Read only library becomes writeable when updated 814347 ALLEGRO_EDITOR ARTWORK It seems like not work ”detailed text checking” on 16.3. 814451 ALLEGRO_EDITOR DATABASE Allegro get crash when run dbdoctor 814496 CAPTURE ANNOTATE Lower level part refdes resets to ? 815150 SIP_RF OTHER sip layout export chips output is not correct 816034 ALLEGRO_EDITOR MANUFACT Backdrill Passes not work from bottom 816065 APD DATABASE Export Libraries with no library dependencies selected creates package symbol without pins. 816426 ALLEGRO_EDITOR SHAPE Dynamic shape not updated when component is unplaced 816616 SCM SYSTEM_OBJECT codesign incorrectly maps primary and secondary codesign object 816686 ALLEGRO_EDITOR TESTPREP Probe Spacing rounds off 3 place decimal to 2 places 816917 SIG_INTEGRITY LIBRARY Issue for loading interconn.iml 816986 ALLEGRO_EDITOR MANUFACT Mfg>NC>Backdrill analysis with passes set at Bottom layer is automatically switching to top, hence failing! 817473 CAPTURE NETLIST_ALLEGRO Backslash (\) is considered as illegal character for netname but it was allow in SPB 16.30.010 817606 SIP_LAYOUT WIREBOND When moving Bondfingers the Via's are sliding too when they should not. DATE: 08-27-2010 HOTFIX VERSION: 015 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 664821 CAPTURE NETLIST_ALLEGRO Improve error messages when netlister finds illegal characters in the pin names 753867 PCB_LIBRARIAN GRAPHICAL_EDITOR PDV crash when graphics from one symbol to another 777559 CAPTURE OTHER Why the Reference designators get lost in project with external references. 777657 CAPTURE PROJECT_MANAGER Archive Project causing Capture to crash 785748 SIG_INTEGRITY OTHER 16.3 SI model library path directives behave inconsistently if the ~pcbenv/env file is present 789529 ALLEGRO_EDITOR EDIT_ETCH Neck Gap changed to Primary Gap when executing Delay Tune command. 791853 SIP_LAYOUT EDIT_ETCH via slide clips to 45 angles near BGA 796604 MODEL_INTEGRIT TRANSLATION ibis2signoise replace V_fixture_min with V_fixture_max based on the value. 797657 CONSTRAINT_MGR CONCEPT_HDL constraints from the brd file are not passed on to the schematic. 802760 ALLEGRO_EDITOR NC nc route not generating the circle correctly 803572 MODEL_INTEGRIT TRANSLATION quad2signoise fail if MODEL name include backquote. 803869 SIG_EXPLORER OTHER Trace parameters form does not update with correct stackup data 804070 ALLEGRO_EDITOR SKILL The skill setting objects not match to all items in CM. 805641 ALLEGRO_EDITOR COLOR Clear all nets fails to remove the custom color on the Color Dialog form 806115 PSPICE MODELEDITOR Cannot generate a Capture symbol from Model Editor because no Capture license. 806196 CONSTRAINT_MGR OTHER Netrev fails with warnings. 806864 CONSTRAINT_MGR CONCEPT_HDL "Selected nets/xnets only" option in CM connected to DE-HDL 807960 ALLEGRO_EDITOR COLOR Click OK to Color Dialog box and Shadow Mode ON/OFF setting will be lost. 808155 F2B DESIGNVARI Variant Editor variant.lst and BOMCompare not the showing the same data 808392 SIG_INTEGRITY OTHER Cross section impedence not calculating for SPB 16.3 with single license for OrCAD PCB Editor 808978 CAPTURE STABILITY Unable to Place > OLE object > Visio drawing file. Capture crashes as well 809163 SCM PACKAGER scm crashing when running export physical 809526 ALLEGRO_EDITOR DRC_CONSTR multi-thread DRC hangs when replacing padstacks 809587 PCB_LIBRARIAN GRAPHICAL_EDITOR PDV crashes during Text Cut/Paste operation in Symbol Editor 809636 ALLEGRO_EDITOR DRC_CONSTR drc update reports incorrect DRC count when run after deleting unused region in constraint manager. 809847 PCB_LIBRARIAN CORE "Auto add SWAP_INFO to chips" problem 810024 ALLEGRO_EDITOR SKILL axlGRPDrwText does not work for left justification 810530 ALLEGRO_EDITOR EDIT_ETCH Sliding vias on differential pair is not selecting both nets 810860 ALLEGRO_EDITOR DRC_CONSTR Improve Update DRC efficiency 811506 CIS ICA Using Capture V16.3 ISR0013 “Save Schematic Part” option is missing in "New Database Part Wizard". 812259 ALLEGRO_EDITOR SCHEM_FTB scm crashing when running export physical- AGAIN 812269 APD WIREBOND Wire diameter and wire profile automatically is changed when executing wirebond add command 812597 PSPICE SIMULATOR Pspice crash. 812655 SIP_LAYOUT IMPORT_DATA Importing Stream data multiple times into a .dra will have inconsistent results, each import is different. 813253 ALLEGRO_EDITOR DRAFTING Datum Dimensioning Crashing Allegro 813265 APD WIREBOND Wire Bond Report fails with wires present that were added with the "Add/Edit Non standard" option. DATE: 08-13-2010 HOTFIX VERSION: 014 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 792354 CONCEPT_HDL CONSTRAINT_MGR Viewing a second net in SigXP from Design Entry HDL constraint manager generates an error 800336 GRE CORE GRE's Plan Spatial crashes Allegro. 801116 SIP_LAYOUT WIREBOND Wirebond -> change characteristics with only wires selected should not modify connected fingers' placement at all. 801463 ALLEGRO_EDITOR EDIT_ETCH The Allegro axlShoveItems SKILL function behaves differently in 16.3 than it does in 16.2. 803049 MODEL_INTEGRIT TRANSLATION quad2signoise cannot translate OpenDrain Model correctly. 803878 ALLEGRO_EDITOR DRC_CONSTR 'Via_At_Smd_Fit' not working correctly when the via fully covers the pin. 804273 ALLEGRO_EDITOR DATABASE Running update DRC gives different number of DRC. 804330 F2B PACKAGERXL Packager is changing the refdes in preserve mode for components in hierarchical block 805335 F2B PACKAGERXL Packager fails reporting empty location values when the location values do exist 805676 ALLEGRO_EDITOR DRC_CONSTR Update DRC hangs while updating differential pair checks with dynamic 805747 SIP_LAYOUT EXTRACT Extracta crashes with this testcase and command file. 806028 ALLEGRO_EDITOR TESTPREP Allegro testprep parameters causes crash 806120 PSPICE NETLISTER “Enable PSpice AA Support for legacy" option results to undefined errors 806182 ALLEGRO_EDITOR SKILL axlPolyFromDB will crash if object is a pin on an unplaced component 807543 ALLEGRO_EDITOR DRC_CONSTR Via at SMD Thru DRC not working correctly in Solaris 808047 SCM SETUP scm not loading all parts from pcb after running brd2asa 808831 ALLEGRO_EDITOR DRAFTING "Oops" command(in dimension angular command) crashes Allegro. DATE: 07-31-2010 HOTFIX VERSION: 013 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 576133 CAPTURE ANNOTATE Annotations in the design getting reset to ? 688692 CONCEPT_HDL GLOBALCHANGE Global Change does not respond to RMB> Done 731045 CIS EXPLORER Double click in CIS explorer places two components 763550 CONCEPT_HDL SKILL nconcepthdl in 16.3 no longer recognizes skill functions that worked in 16.2 764130 CONSTRAINT_MGR OTHER Export Excel from CM hangs/crashes Allegro on attached design 766750 ALLEGRO_EDITOR INTERACTIV Request to enable datatips when constraint manager is open and a command is active 774466 CAPTURE CORRUPT_DESIGN DSM0008 - Unable to open design in 16.3 777862 CIS PLACE_DATABASE_P Absolute path in field Schematic_Path causing incorrect display property 782370 CONCEPT_HDL OTHER CreferHDL $XR hyperlinks do not work in PDF Publisher - they did in SPB16.2 783036 SIG_INTEGRITY SIGNOISE Problem for Waveform saving with -w option in signoise command. 784205 CONCEPT_HDL CORE Schematic block generated from SCM needs to have DIFFERENTIAL_PAIR property on the ports 786387 CAPTURE OTHER Update cache does not update the parts on schematic 786560 CAPTURE NETLISTS Sqare bracket [] is not allowed in PADS netlist. 786808 SIG_EXPLORER OTHER RMB > Via_Model_Name doesn't display the generation param of the via. 787414 CAPTURE PROPERTY_EDITOR Part value can’t be moved on schematic if a part has been copied to a new design and not saved yet. 791965 CONCEPT_HDL CORE group move should not snap to center of group 792126 CAPTURE PROPERTY_EDITOR Attempt to change display for occ prop resets 794900 CAPTURE NETLISTS Attached design is not getting netlisted in V16.3. It works fine in V16.2 795914 PSPICE SIMULATOR Getting RPC Server Unavailable Error 795997 ALLEGRO_EDITOR TECHFILE crash when importing dcf file 796124 CONCEPT_HDL CORE Messages overflow console 796168 CONSTRAINT_MGR CONCEPT_HDL Create ECSet in DEHDL CM moves focus to DEHDL 796378 ALLEGRO_EDITOR PADS_IN Pads_in has error while translating PADS 2007 asc file 796658 APD OTHER Allegro can not import the property section of 3rd party netlist correctly. 796926 CONSTRAINT_MGR OTHER Importing Custom Worksheet file does not overwrite the Description field. 797387 SCM SCHGEN Increasing the grid units from 25 to 100 breaks the bus into bits on the generated schematic. 797529 SIP_LAYOUT IMPORT_DATA import BRD to SIP fails if database has partitions. even if only silkscreen and documentation exist 797634 SIP_LAYOUT DIE_EDITOR rat control buttons in edit die mode are invisible until user selects an action 797663 SIG_EXPLORER OTHER Current probe could not get from sigxp left symbol panel. 798118 SCM REPORTS SCM report not resolved with CCR 697709 798464 ALLEGRO_EDITOR SKILL axlDetailLoad not filling shapes in 16.3 s10 798980 ALLEGRO_EDITOR DATABASE Unable to open board file as it fails with a error message Found bad data pointer, run dbdoctor. 799445 PSPICE MAG_DESIGNER Magnetic Parts Editor crashes while saving newly created Magnetic component 799539 CONCEPT_HDL COMP_BROWSER PPT Options settings lost when cancel done in PPT Options form 799957 CAPTURE CORRUPT_DESIGN Capture crashes while doing save as in 16.3 800280 SIP_LAYOUT WIREBOND Swappoing Dies in the die Stack will cause the bondfingers to move and create DRCs 800542 POWER_INTEGRIT SIMULATION Multi Node Simulation does show actuall waveform 800695 CONCEPT_HDL CORE Genview changed behavior in 16.3 HF 11 breaking the design hierarchy 800751 ALLEGRO_EDITOR DFA DFA placement does not understand package keepout 801017 ALLEGRO_EDITOR REPORTS APD Crash when creating Unused BB Via Report 801043 SIG_INTEGRITY OTHER SigNoise Case Update seems to check ActiveDesignLink value incorrectly. 801433 ALLEGRO_EDITOR MODULES selected figures do not end up in the module 801705 ALLEGRO_EDITOR SYMBOL Shape symbol was specified with RegularPAD of the PAD stack become "Null". 802319 ALLEGRO_EDITOR SHAPE Shape status cannot be changed to smooth using suppress pads. 802474 CONCEPT_HDL LWB-HDL Testbench generator not working in Linux 802887 ALLEGRO_EDITOR OTHER Adding the No_Shape_Connect property to via causes the application to crash. 803393 SIP_LAYOUT DXF_IF Cannot generate a dxf file DATE: 07-16-2010 HOTFIX VERSION: 012 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 757157 CONCEPT_HDL CORE Zoom (using SHIFT + mouse wheel) to work such that the tool zooms based on cursor location 766639 ALLEGRO_EDITOR EDIT_ETCH via structure disappearing after selecting place manual hide icon. 770910 PSPICE PROBE Printing from probe yields text label with too small size 773603 SIG_INTEGRITY SIMULATION The characteristic of S-parameter model is different. 774363 CONCEPT_HDL CORE hier_write didn't report error. 776991 CONCEPT_HDL CORE The Wire> Bus Name command does not use the Net Name font setting 781965 PSPICE PROBE Unable to add trace expression with small letters 782847 SCM PACKAGER PKG-10002 - Cannot associate a logical part from chips.prt 783245 SIG_EXPLORER EXTRACTTOP extracting net with trace on plane layer giving unconnected topology 785320 LAYOUT TRANSLATORS L2A translation fails with error "output directory is not writable". 785401 SIG_INTEGRITY OTHER The "View Geometry" or sigxsect command is not working in SQ 16.2 785715 ALLEGRO_EDITOR PADS_IN PADS_IN fails to convert some components on Bottom Layer and adds two components at same location 785868 SIG_INTEGRITY OTHER Unable to generate Parallelism report as the report seems to have hung the SQ Session. 788523 CONCEPT_HDL CORE selecting QuickPick toolbar button should not reset canvas zoom 789333 CONCEPT_HDL CORE Font colors not being used as set in the SITE .cpm file 789348 ALLEGRO_EDITOR EDIT_ETCH Via Structures removed from database when switching to any App mode from Placement App mode 789473 SIG_INTEGRITY OTHER Via delay is not included when t-point is at the via 789744 ALLEGRO_EDITOR SHAPE Update Symbol with cline at symbol level do not connect clines properly 790170 F2B DESIGNVARI Function of Variant Editor and Annotate schematics 790811 APD ARTWORK Some Void shifts by the artwork output. 791371 ALLEGRO_EDITOR REPORTS Dangling line with cpoint not reported in the dangling lines report. 791486 CAPTURE PLUGIN_INTFACE Unable to open a PSpice Project by double clicking the .opj file, if Capture is already open 791663 CIS RELATIONAL_DB Relational view doesn't appear when capture opens second time 791690 ALLEGRO_EDITOR EDIT_ETCH etch editing/routing in placement mode, allegro looks for all libraries adding delay in routing. 791720 ALLEGRO_EDITOR DATABASE Color Net param file does not have some nets with special characters in the Net name. 791987 ALLEGRO_EDITOR PADS_IN PADS Translation fails with no error message 792232 ALLEGRO_VIEWER OTHER Import parameters not bringing in plane colors in allegro viewer 792559 ALLEGRO_EDITOR DATABASE Error when executing refresh symbol command 792923 ALLEGRO_EDITOR OTHER sted fails Can't open STED stroke file ~pcbenv/allegro.strokes 793358 SPECCTRA PARSER When I try to invoke Allegro PCB Router it fails to invoke with errors. 793605 CONSTRAINT_MGR OTHER Importing custom consmgr.wcf file crashes Allegro. 793955 ALLEGRO_EDITOR DRC_CONSTR add connect launch signoise even so electrical drc are all at off 794748 LAYOUT TRANSLATORS import fails with message not valid Allegro subcls 794775 ALLEGRO_EDITOR SCHEM_FTB Import logic runs forever or get a netrev error without any explanation 795261 CAPTURE NETLISTS Create netlist hangs in SPB16.3 795364 CONSTRAINT_MGR OTHER bookmarks are not getting saved in CM 795410 APD BGA_EDITOR Using the Edit > BGA tool I cannot get it to modify the pin numbering of a BGA 795501 PSPICE PROBE Unable to see the Multiple Mark-Labels in Probe 795761 ALLEGRO_EDITOR DRC_CONSTR Design is crashing while executing Tools > Update DRC 795770 ALLEGRO_EDITOR DATABASE void moves when upreving from 15.7 to 16.3 796026 CONCEPT_HDL CHECKPLUS CheckPlus reports text overlaps inccorectly on Linux 796092 MODEL_INTEGRIT TRANSLATION ibis2signoise crash if Submodel section exist next to Component section. 796361 SIG_EXPLORER OTHER When dml file is loaded "Illegal format in device file" is outputted. 796366 CONCEPT_HDL CORE UI windows in DEHDL are scattered 796590 APD DRC_CONSTRAINTS CM Hole Spacing rule always set to 1905 in a new design. 796858 ALLEGRO_EDITOR DATABASE Deleting layers that has only vias moves etch from other layer on it and prevents the layer from being deleted. DATE: 06-25-2010 HOTFIX VERSION: 011 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 644128 ALLEGRO_EDITOR MANUFACT Enhance Backdrill for HDI Buried Vias 743746 ALLEGRO_EDITOR MANUFACT Sub-laminate back drilling -Arbitrary from-to layer drill capability needed 773066 CAPTURE EDIF PinSwap information written in EDIF does not back to Capture schematic 775690 CAPTURE STABILITY Design is not properly translated in 16.3 782854 ALLEGRO_EDITOR COLOR Component Keep Out for the Top & Bottom layers not showin in the Color Dialog box, only ALL shows. 784439 SIG_INTEGRITY OTHER CM of 16.2 recognizes the differential pair nets as Xnet. 785135 CONCEPT_HDL CONSTRAINT_MGR Applying an ECSet to a diff pair crashes Constraint Manager 785179 SCM OTHER Changing a differential interface signal to local corrupts the con file and ASA is not able to load 785332 SIP_LAYOUT LEFDEF_IF unable to def in to sip layout 785423 SCM SCHGEN Schematic having incorrect connectivity 786858 SIG_INTEGRITY SIGWAVE want to select license at launching sigwave 786871 ALLEGRO_EDITOR SHAPE Allegro dynamic shape not updating 786957 CAPTURE MACRO If an off page connector is renamed using macro the net name attached to it is not getting changed 787003 CONCEPT_HDL CONSTRAINT_MGR olecs crash in CM when rename librray defined diffpairs on this design. 787087 ALLEGRO_EDITOR DRC_CONSTR Diff pair Static Phase tolerance Error 787174 ALLEGRO_EDITOR MANUFACT Reading filmsetup.txt file crashes Allegro 788521 ALLEGRO_EDITOR DRC_CONSTR There is a difference of DRC between SPB16.2 and SPB16.3. 788652 F2B DESIGNVARI Variant Editor cross highlights incorrectly to Concept 788658 CAPTURE NETLIST_OTHER OrIntegra.dll netlist has inconsistent behavior 788718 ALLEGRO_EDITOR DATABASE Board crashes upon deleting Cline segments within BGA using Allegro PCB Design XL License. 789206 ALLEGRO_EDITOR SYMBOL Merge shape option causes attached *.dra file to crash 789324 CONCEPT_HDL CHECKPLUS CheckPlus output producing wrong values 790049 SIP_LAYOUT EXPORT_DATA Offset wire tack points disables wire in AIF Output 790503 ALLEGRO_EDITOR SHAPE Shape Void not correct 790567 SIP_LAYOUT TILING unable to run the ndw tile die generator 790622 ALLEGRO_EDITOR SKILL line width of internal segments within hatched shapes not correct when created using SKILL 791075 SIP_LAYOUT EXPORT_DATA The shape that connects Merged Bond Fingers is missing in the DXF output. DATE: 06-11-2010 HOTFIX VERSION: 010 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 701724 CONCEPT_HDL CORE Page Down (PgDn key) Key is unresponsive 722773 ALLEGRO_EDITOR DATABASE How can i add DUMMY NETS to a Net Class ? 767874 ALLEGRO_EDITOR OTHER Component Geometry/Pin number not imported. 769644 ALLEGRO_EDITOR SCRIPTS Why Command line script in non graphical mode prints everything to the screen when working with Windows? 778086 SIG_INTEGRITY SIMULATION extracted net yields unrealistic resuts +/- 100v swings 778915 ALLEGRO_EDITOR OTHER Export library dumps symbols with mechanical pins instead of connect pins 779119 PSPICE ENVIRONMENT MC Analysis does not seem to honor Custom Distribution 779161 ALLEGRO_EDITOR OTHER Getting error-"illegal arguments passed to a dba routine" when connecting CLine to via 779335 SIG_INTEGRITY SIMULATION HSPICE sim from PCB SI caused netlist error. 780314 SCM UI ASA crashes on paste special. 780345 CONCEPT_HDL CORE Pins look garbled when part is vertically mirrored 780811 ALLEGRO_EDITOR SKILL Request 1k limit of SKILL API be removed. 781111 SIP_LAYOUT IMPORT_DATA Import Brd to SiP failed 781259 CONSTRAINT_MGR TECHFILE Import tech file crashes Allegro 781287 ALLEGRO_EDITOR DATABASE dbdoctor removes tespoints from odd angle clines leaving V/L drc 781331 ALLEGRO_EDITOR SCRIPTS Script executed by command redirection operators is giving different o/p for v16.01 and 16.3 781647 ALLEGRO_EDITOR MENTOR mbs2brd is defining extra additional testpoint that is not present in Mentor database 781650 ALLEGRO_EDITOR DRC_CONSTR Update DRC hangs while updating differential pair checks with dynamic phase tolerance added from the logic import 781665 PSPICE DEHDL_NETLISTER Error simulating delay component 781688 CONSTRAINT_MGR ANALYSIS Application hangs on Solaris when executing DRC update 781799 ALLEGRO_EDITOR OTHER Unexpected results when exporting and importing text parameters 781922 ALLEGRO_EDITOR SHAPE Pin doesn't connect as a thermal. 782124 CAPTURE PLUGIN_INTFACE Bias point display not getting updated for projects on network 782415 SPIF OTHER File > Export > Router takes 5 hours to create a .dsn in windows....1.25 hours in Linux. 782566 ALLEGRO_EDITOR PLOTTING It seems like not work PLOT parameter "Auto Center" on tight paper size. 782628 SCM NETLISTER Connection change not updated in the Verilog Netlist 783059 ALLEGRO_EDITOR DRAFTING Create Detail with "filled pads disabled" doesn't work with irregular shape pad. 783142 SIP_LAYOUT IMPORT_DATA import bga text in on connector crashing sip layout 783222 FLOWS PROJMGR Edit Physical and Spacing constraints 783241 ALLEGRO_EDITOR PAD_EDITOR Pad Designer hangs when attempting to save to file. 783283 SCM IMPORTS scm crashing with import physical 783301 SIP_LAYOUT WIREBOND All Bondfingers not sliding along path. 783496 ALLEGRO_EDITOR MODULES Problem of module placement. 783813 SIP_LAYOUT BGA_GENERATOR Request to add new JEDEC BGA sizes to the BGA wizards standard JEDEC pulldown menu. 784441 APD OTHER Users cannot delete layer even everything was deleted 784639 ALLEGRO_EDITOR DATABASE both dbdoctor and allegro are crashing while opening this database 785100 CONCEPT_HDL CREFER Cross Referencer must not call Unix command on Windows platform 785385 ALLEGRO_EDITOR MANUFACT Allegro Crashes when using Datum Dim with Shapes. DATE: 05-28-2010 HOTFIX VERSION: 009 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 758913 APD OTHER uncheck default check buttons through options/preferences 763566 PCB_LIBRARIAN PTF_EDITOR The ptf command in batch mode always returns "abort" 763662 ALLEGRO_EDITOR INTERACTIV Place replicate update creates numerous DRC on win platform 771088 CONCEPT_HDL COMP_BROWSER QuickPick adds incorrect property value when ppt optionset file is used 772285 MODEL_INTEGRIT GUI Model contains recursive calls fater port rename reorder funtion is performed on it. 774070 ALLEGRO_EDITOR DRC_CONSTR Allegro crash when sliding connections. 774880 ALLEGRO_EDITOR INTERACTIV Place replicate stops with No available buffer identifiers. 775443 APD EDIT_ETCH The routing of DIff Pairs when transitioning from a region needs to be smoother. 776022 ALLEGRO_EDITOR INTERACTIV Allegro crashes when we use Ctrl+Click in Etch Edit mode for selecting a Cline Segment in Allegro PCB Design L 776151 ALLEGRO_EDITOR REPORTS Shape report incorrectly lists thermal connections for SMD,Via and Through all as Through. 776190 ALLEGRO_EDITOR INTERACTIV place replicate crash; select polygon zoom points 776284 PSPICE STABILITY 16.3 design crash while simulating the design 777556 SPECCTRA CHECK interlayer clearance output drc even so layers are separated by a power layer 777689 ALLEGRO_EDITOR SHAPE Shape do not void if Curved Fillets are used 777698 CIS RELATIONAL_DB CIS 16.3 ISR s007 - Relational feature doesn't work 778042 CAPTURE PRINT/PLOT/OUTPU Some text are not searchable in Capture generated pdf 778350 ALLEGRO_EDITOR SHAPE Multiple Drill on pad gets round void instead of rectangular 778356 ALLEGRO_EDITOR SKILL Duplicate Vias with axlDBCreateModuleDef 778782 ALLEGRO_EDITOR OTHER Display-measure and axlAirGap incorrectly report no air gap for multiple drill pin 779146 ALLEGRO_EDITOR OTHER Moving component crashes Allegro 780213 ALLEGRO_EDITOR DATABASE Design saved in GXL when opened in XL gives misleading message. 780773 ALLEGRO_EDITOR SHAPE No DRC displayed when Place Bounds are edge to edge DATE: 05-14-2010 HOTFIX VERSION: 008 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 697699 CONCEPT_HDL HDLDIRECT SCM Verilog output contains the line “defparam .SIZE 734169 ALLEGRO_EDITOR PLACEMENT Wildcard asterisk character giving "illegal char(s) in refdes entry." error in quickplace. 738970 SIG_INTEGRITY GEOMETRY_EXTRACT power bus issue with SSN simulation when device is on bottom 744762 CONCEPT_HDL OTHER Connection dot sizes do not match on printout vs. screen 750371 MODEL_INTEGRIT GUI Model name in physical view cann't match the model in right workspace 757024 CAPTURE STABILITY Capture crashes while exporting to EDIF 759094 CONSTRAINT_MGR INTERACTIV One member of a diff pair will show Analysis Failed when analyzing the design. 760178 ALLEGRO_EDITOR EXTRACT Crash Allegro when executing extracta command for big size design(size of .brd 761391 SIG_EXPLORER OTHER Incorrect rise time 762402 ALLEGRO_EDITOR MANUFACT When photoplot(RS274X) of MM unit was loaded, shape was broken. 762783 SIG_EXPLORER INTERACTIV sigxp - coupled tline on stackup layer should show solved impedance 763150 ALLEGRO_EDITOR OTHER Request - IPC356 output truncate the padstack size to fit into the columns 59-62 and 64-67 763556 SIP_LAYOUT ASSY_RULE_CHECK Assembly Rules Checker is displaying an array of confusing DRC's on a Soldermask shape. 764399 SPECCTRA ROUTE Manually routed trace in Allegro are ripped OFF after routing in SPECCTRA using Route > Route Editor. 764475 SIG_EXPLORER INTERACTIV topologies from earlier versions cannot be opened in 16.2 on a machine 765287 ALLEGRO_EDITOR PAD_EDITOR attempting to open padstack fails with - database has a non-recoverable corruption. 766041 ALLEGRO_EDITOR OTHER Auto B/B via generator incorrectly defines some BB vias 766153 ALLEGRO_EDITOR SKILL Allegro crashes when trying to extract padstack information 766611 ALLEGRO_EDITOR EDIT_ETCH slide creates DRCs in ARK area 767041 CONCEPT_HDL CORE The tap command failed because the specified tap body CTAP is invalid 767146 FLOWS PROJMGR Project manager open last open .cpm in 15.7 version not in 16.3 767526 FLOWS PROJMGR Project Manager customization does not work 767671 APD DATABASE Crash creating cline with axlDBCreatePath() on this database. 767951 ALLEGRO_EDITOR DATABASE color net param file omits nets with bus brackets in the name 768168 CONCEPT_HDL CORE Fontsize on instances changes when doing backannotation 768207 CAPTURE STABILITY Capture crash while editing properties 768734 CAPTURE PROPERTY_EDITOR Properties of title block are not getting editted through spread sheet. 768832 APD DRC_CONSTRAINTS Following Performance Advisor instructions results in much longer DRC check time. 768990 F2B PACKAGERXL RFSIP architect 16.3 85Y Schematic to SiP fails due to softinclude in cds.lib file this problem does not occur on 16.2 769097 SIG_INTEGRITY GEOMETRY_EXTRACT Sip Digital SI-Bus Simulation function will shut down auomatically when it is running 769235 SPIF OTHER need to be able to remove mbs_spif* properties added by mbs2brd 769326 CONSTRAINT_MGR DATABASE Length by Layer crashing 769336 ALLEGRO_EDITOR TESTPREP testprep density - returns Unable to add the PROBE_DENSITY subclasses. 769458 ALLEGRO_EDITOR OTHER SMD Jumper has a problem about the connection point when using the Add Jumper 769845 ALLEGRO_EDITOR EDIT_ETCH Diffpair routing out affected by line to line spacing rule. 769934 SIP_LAYOUT WIREBOND Duplicate Finger Name. 770006 ALLEGRO_EDITOR OTHER Ratsnest_schedule[Power_AND_Ground] can not show figure without move symbol. 770125 ALLEGRO_EDITOR DATABASE PCB SI GXL Via Labels grayed out on formand labels not visible on the canvas 770212 ALLEGRO_EDITOR DRC_CONSTR Incorrect Etch Turn under SMD pad DRC error on this board 770230 ALLEGRO_EDITOR ARTWORK Artwork fails to suppress unconnected pads on pins with the net_short property. 770233 ALLEGRO_EDITOR MANUFACT Fillets are not behaving as intended. 770442 SCM PACKAGER Error during Export Physical - The subdesign block instances ares not updated with reuse properties 770556 CONSTRAINT_MGR ANALYSIS PCB Editor's Constraint Manager not updating custom constraint cell. 770861 ALLEGRO_EDITOR PADS_IN PADS translation fails with no error message 770872 SIG_INTEGRITY OTHER Opening Orcad PCB Editor for this board takes Performance License as well 771117 ALLEGRO_EDITOR DRC_CONSTR Allegro PCB Editor crashes on Update DRC-16.3/hotfix006 771181 ALLEGRO_EDITOR PLACEMENT Component deleted completely from board file after we Mirror and rotate them while moving them. 771256 ALLEGRO_EDITOR DRC_CONSTR Update DRC consumes system memory and crashes allegro after approx 30 minutes 771423 ALLEGRO_EDITOR SHAPE Shapes - Update to Smooth - Low on available memory please exit the program. 771456 ALLEGRO_EDITOR EDIT_ETCH Allegro 16.3 crashes when using arrow keys 771719 PSPICE MODELEDITOR Can not generate a DEHDL symbol from Model Editor, because no Capture license. 771765 ALLEGRO_EDITOR PADS_IN PADS translation fails to translate symbol 771766 ALLEGRO_EDITOR DRC_CONSTR Moving certain components takes a long time on this board database. 771815 SIP_LAYOUT IO_PLANNER SiP OA co-design flow does not allow a save to the .sip file after modifications in IOP 773072 SIP_LAYOUT ASSY_RULE_CHECK wire to wire same profile 773126 CONSTRAINT_MGR UI_FORMS Constraint Manager "Value Filtering" for Topology Schedule is missing TEMPLATE and "UserDefined" 773179 ALLEGRO_EDITOR PAD_EDITOR pad_designer crashed when attemting to delete internal name layer. 773229 ALLEGRO_EDITOR OTHER Netrev never end importing netlist generated from Capture CIS 773329 ALLEGRO_EDITOR MANUFACT Allegro closes when performing a Linear dimensioning and then selecting the undo icon. 773483 ALLEGRO_EDITOR MODULES place module problem 774036 ALLEGRO_EDITOR INTERACTIV Rats not shown after move->mirror command 774170 ALLEGRO_EDITOR DATABASE DBDOCTOR fixes Error but it reappears and Artwork fails 774602 SCM OTHER ASA crash while working with hierarchy 774643 CONCEPT_HDL CORE DEHDL crash on edit of attributes 775201 ALLEGRO_EDITOR SKILL Color palette can only be changed one time using skill commands 775815 SIP_LAYOUT WIREBOND Unused wire profile once purged using wire profile editor are still available in CM and Color dialog 775826 SIP_LAYOUT WIREBOND Cannot change the Wire Profiles on the wirebonds in this design 775842 SIP_LAYOUT WIZARDS Die text in wizard is changing DIE location when origin set in DIE text file is other than 0, 0 DATE: 04-23-2010 HOTFIX VERSION: 007 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 721859 ALLEGRO_EDITOR OTHER update shape to smooth creates tmp file on remote file server working dir why? 740201 SPECCTRA_MENT_ IMPORT Wrong stackup order after translating from mbs2sp 744797 SIP_LAYOUT OTHER Cannot Copy a connector (IO) symbol in APD and SiP tools 747831 CIS CONFIGURATION There is a delay of 5 to 10 mins in opening SQL database in V16.2 and V16.3. It is fine in V16.0. 747848 CIS CONFIGURATION Unable to configure CIS with Oracle database due to Capture crash. 751372 CAPTURE OTHER Copy / Paste Issue in capture 16.3 757434 ALLEGRO_EDITOR MODULES Allegro hangs the board file after creating Placement Replicate circuit. 759906 CIS PART_MANAGER Property copy from one to several parts doesn't work 760154 PSPICE NETLISTER Model parameter (Tj) is not affecting Smoke Analysis result 761177 CIS OTHER Error Message - Memory exhausted 762602 CIS EXPLORE_DATABASE CIS doesn't open datasheet for parts if it is not stored at default Capture location. 763677 APD EDIT_ETCH The "Via to Via Line Fattening" tool is inconsistent in which clines are changed. 763715 CAPTURE NETLIST_OTHER A long pin name gets truncated upto 31 characters when the wirelist is created. 763878 CONSTRAINT_MGR DATABASE Why Pinpairs disappear after closing Constraint Manager? 764020 CAPTURE NETLISTS Usernetl.dll has changed between 16.2 and 16.3 764101 APD EDIT_ETCH Perpendicular routing through a Region does not work when the region segment is drawn at an angle. 764200 ALLEGRO_EDITOR DRC_CONSTR Via at smd fit drc on a via that is placed fully inside the padstack having custom pad 764903 PSPICE ENVIRONMENT 'Run in Resume Mode' does not work in SPB 16.3 765206 F2B PACKAGERXL Unable to feedback subsequent pin swaps from Allegro 765319 APD DRC_CONSTRAINTS Identical Constraints in Performance Advisor question 765541 SIP_LAYOUT SHAPE Set via oversize value to 3 in dynamic shape instance parameters will make overlap shape. 766147 APD EDIT_ETCH Resize/Respace Diff Pairs does not work on 45 and off angle 766337 SIG_INTEGRITY GEOMETRY_EXTRACT Geometry of Via model Extracted from board file is not identical to Original Via geometry design 766443 ALLEGRO_EDITOR PADS_IN unable to translate PADS ascii to brd in 16.3 766581 CIS CONFIGURATION In 16.3 capture.exe remains memory-resident after exit 767161 ALLEGRO_EDITOR SHAPE The behavior of Add Fillet command is different by Hotfix version. 767217 SIP_LAYOUT IMPORT_DATA The Die-Text In wizard and it is crashing on the "Finish" step. 767598 SIP_LAYOUT WIREBOND Can't wirebond SIP designs as it just hangs. 767832 ALLEGRO_EDITOR DRC_CONSTR Reducing Design Accuracy updates Physical Diffpair constraints wrongly 768822 ALLEGRO_EDITOR SKILL axlSetParam return value is divided by 10 to the power of the design accuracy. 769150 CIS PART_MANAGER Update All part Status on a group changes “Do Not Stuff” status to “Stuffed” in V61.3_ISR_5. DATE: 04-09-2010 HOTFIX VERSION: 006 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 745241 CONSTRAINT_MGR TECHFILE Importing a tcf file automatically enables On-Line DRC. 752587 ALLEGRO_EDITOR PLACEMENT Uppercase File name(XX.mdd) for Placement replicate update on Linux. 753626 CONCEPT_HDL CORE newgenasym error while saving the hierarchical block symbol 753894 CAPTURE OTHER Case sensitive version control S/W 754487 RF_PCB OTHER Various asymmetrical clearance problems uncovered - calculation issues? 758272 CONSTRAINT_MGR UI_FORMS Entering values on the Min/Max Propagation Delays worksheet hangs the application. 758911 PSPICE PROBE Pspice crashes while exporting probe data using our sample project 759871 CAPTURE PROPERTY_EDITOR Save option in Right Mouse Click on property editor of nets doesn't saves all the changes. 759890 SPECCTRA ROUTE Specctra autorouter ignoring prerouted nets 760067 ALLEGRO_EDITOR SHAPE Dynamic Shape not getting filled on board with odd angle placement and routing 760284 CONCEPT_HDL CORE Update Sheet Variables turns of the grid 760480 MODEL_INTEGRIT OTHER Message open clipboard failed when trying to open the rename/reorder dialog in Model Integrity 760667 ALLEGRO_EDITOR PADS_IN The pads_in.exe translate incorrect drill shape from PADS 2005 ascii database. 760741 ALLEGRO_EDITOR MENTOR mbs2brd does not work in 16.3 but works in 16.2 760810 CONSTRAINT_MGR INTERACTIV Deleting Region Deletes NCCs 761114 PSPICE PROBE Refresh issue in Display > Cursor window 761180 ALLEGRO_EDITOR DRC_CONSTR Via_at_smd not working for custom shaped padstacks. 761305 SPIF OTHER Allegro crash when seleting any of the Route - PCB Router - submenu items. 761376 ALLEGRO_EDITOR PAD_EDITOR Wizard_Template_Path is not considered for symbol template look-up ? 761416 ALLEGRO_EDITOR DATABASE Allegro crash on chaning the subclass for group of clines 761492 ALLEGRO_EDITOR SKILL about axlTransformObject function 761518 F2B PACKAGERXL about mismatch library path between cds.lib and actual 761737 ALLEGRO_EDITOR OTHER Running Dbdoctor after executing Skill is giving symbol fit error for the .dra file 762155 ALLEGRO_EDITOR SYMBOL Updating a symbol changes the netname of the cline resulting in drcs. 762181 ALLEGRO_EDITOR OTHER Allegro netrev crashes for long device name in PST* files 762316 ALLEGRO_EDITOR MANUFACT Allegro disappears on Adding dimensions for the symbol file 762792 ALLEGRO_EDITOR PADS_IN PADS_IN fails for SPB 16.3 763108 ALLEGRO_EDITOR SHAPE Z-copy shape create an error like VOID boundary may not cross itself 763134 SIG_INTEGRITY SIMULATION Bit 7 of a simulation is out of sync with rest of bus. It should be the same for all bus values. 763149 CIS GEN_BOM CIS BOM in V16.3 is not correct if database has Quantity field and its value is 0. 763296 ALLEGRO_EDITOR REFRESH The error was happened while doing the SUM 763303 ALLEGRO_EDITOR OTHER SMD Jumper has a problem while using the Add Jumper 763315 ALLEGRO_EDITOR PADS_IN pads_in got error message WARNING ERROR(SPMHDB-205) 763354 ALLEGRO_EDITOR PADS_IN Auto suppress redundant shape while using pads_in translator 763428 ALLEGRO_EDITOR PADS_IN enhance pads_in.exe translate spacing and physical rule into Allegro. 763446 ALLEGRO_EDITOR REPORTS missing fillet is reporting pad without drill 763448 ALLEGRO_EDITOR DRC_CONSTR Performance advisor shows Cset as unused nets when it is assigned to Diff pairs or xnets. 763586 ALLEGRO_EDITOR DATABASE Allegro rounds off the value after decimal in CM 764077 CONCEPT_HDL CHECKPLUS The output predicate in the Graphical environment is not always returning the pin object for an output pin. DATE: 03-26-2010 HOTFIX VERSION: 005 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 599819 SIP_LAYOUT 3D_VIEWER display soldermask by default in the 3d viewer 735992 CONCEPT_HDL CORE Create Test Schematic does not use the correct package type 743787 SIG_EXPLORER OTHER 16.3 SigXP crash if sigxp.run created by previous version exist. 746320 CAPTURE NETLIST_ALLEGRO Remove Semi-colon from invalid pin-name check during netlisting 746444 ALLEGRO_EDITOR OTHER show element fails to display info on a via if it is in a module. 746726 SIG_INTEGRITY SIGWAVE Save As and Open Dialogs open in last saved directory 750080 CAPTURE NETLIST_ALLEGRO Improve error message ERROR(SPCODD-390) 750606 SIP_LAYOUT ASSY_RULE_CHECK Wire to BF same profile check 751492 CAPTURE FPGA Option to swap the pin-numbers rather than their locations in the Schematic after back-annotation 753834 CIS LINK_DATABASE_PA unable to link multiple database part 753990 F2B PACKAGERXL Delay in opening the subdesign tab in the Export Physical setup in SPB 16.3 754328 LAYOUT TRANSLATORS L2A gives error Subclass name TOP not valid Allegro subcls with s029 hotfix 754434 CONSTRAINT_MGR OTHER allegro crashes when deleting matched group 755111 ALLEGRO_EDITOR INTERACTIV "ALT_SYMBOLS_HARD TRUE" property does not work when I mirrored symbol using move command in 16.3. 756131 PSPICE SIMULATOR Capture crashes while re-running simulation 756148 PSPICE PROBE Zoom Area in Probe Window does not work for digital signal in SPB163 756169 SIG_EXPLORER OTHER Signal Explorer crashing due to sigsimcntl.dat 756176 PSPICE PROBE Trace color is wrongly interpreted in PSpice probe window. 756224 SIG_INTEGRITY SIMULATION Simulation aborts reporting that VIA models have changed 756281 ALLEGRO_EDITOR OTHER Why *.sav file cannot be recovered from PCB Editor utilities? 756673 SIP_LAYOUT ASSY_RULE_CHECK Running ADRC Metal to metal checks causes false X-D DRCs, cannot clear them and trying crashes the tool 756918 ALLEGRO_EDITOR OTHER Allegro angular dimensions working incorrect in 16.3 756932 ALLEGRO_EDITOR CREATE_SYM Create symbol fails with error duplicate pin number 756976 ALLEGRO_EDITOR SKILL axlChangeWidth always return nil in Allegro version 16.3 757000 PSPICE NETLISTER Incorrect Hierarchical Format Netlist created 757406 APD OTHER Implement Segment over void features in APD L 757624 SIG_EXPLORER OTHER Sigxp runtime error when simulation is run and exit without saving the topology 757820 ALLEGRO_EDITOR SHAPE Shape does not void to hole if there is no pad 758009 ALLEGRO_EDITOR OTHER Export > Library (MECH_SYM) adds a new subclass NCROUTE_PATH, data moved from one subclass to another. 758022 CAPTURE DRC Capture crash while running DRC with “Run Physical Rules” checkbox. 758190 ALLEGRO_EDITOR PAD_EDITOR PCB Editor crashing on pin move in this design 758374 F2B DESIGNVARI Problem with Mechanical part in Variant Editor 758471 SIG_INTEGRITY OTHER Differential impedance does not change on changing the etch effect values. 758490 CIS CRYSTAL_REPORTS Different crystal report output in 16.3 than from 16.2 758498 CAPTURE NETLISTS PCB Editor netlister hangs 758584 APD SHAPE Shape not voiding all elements 758886 ALLEGRO_EDITOR REPORTS Total number of nets is wrong into Testprep Report 759146 ALLEGRO_EDITOR SKILL The title is not displayed in the form by the version. 759339 ALLEGRO_EDITOR ARTWORK artwork output fails by SPB16.x. 759591 ALLEGRO_EDITOR SKILL axlSetParam fails and does not round the value as indicated by the warning message 759816 CONSTRAINT_MGR OTHER Allegro Hangs when double click on a Bus in CM 759947 APD OTHER Need an a way to convert Lines into Clines 760353 ALLEGRO_EDITOR MANUFACT Allegro crashes and creates a .sav file on running the silkscreen command from Manufacture > Silkscreen 760432 ALLEGRO_EDITOR PARTITION Unable to remove fixed property after partition import 760638 ALLEGRO_EDITOR PADS_IN pads_in translator can not handle " PINPAIRGROUP ". 760734 ALLEGRO_EDITOR SHAPE Different therma contacts on rotated partsl 761436 CAPTURE NETLIST_ALLEGRO SPCODD-53 Error when creating netlist with PACK_SHORT DATE: 03-12-2010 HOTFIX VERSION: 004 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 689495 ALLEGRO_EDITOR DATABASE corrupt database 725944 SIG_INTEGRITY GEOMETRY_EXTRACT xtalk make allegro freeze and never give hands 732604 SIP_LAYOUT SHAPE Shape Issue - added shape will not clear around other elements. 740106 PSPICE NETLISTER The "Enable PSpice AA Support for Legacy" option does not give the Desired Monte Carlo results 744259 SCM UI Signal order reversed when a Vectored Signal name is renamed in reverse 745554 SIG_INTEGRITY GEOMETRY_EXTRACT Time to get Xtalk simulation result in 16.2 is lower than acceptable by comparing the time in 15.7 745595 RF_PCB FE_IFF_IMPORT import iff RF_PCB give an empty block 747133 CAPTURE STABILITY ERROR [DSM0006] Unable to save 747679 CAPTURE STABILITY Trying to Save the Design in 16.2 format gives DSM0006 Error and crashes Capture 750460 CIS FOOTPRINT_VIEW 3D footprint viewer doesn't shows the footprints 750777 SIG_INTEGRITY OTHER Trace impedance showing wrong 751424 ALLEGRO_EDITOR DRC_CONSTR Unexpacted DRC for Shape to Route Keepout 751897 SIP_LAYOUT SPECCTRA_IF Radial Router crashing SiP tool 752029 SCM OTHER Cross probing not working between SCM and Allegro Editor in Linux Environment 752450 APD PADSTACK_EDITOR APD crashes when selecting a User Definable Mask Layers. 752581 PSPICE PROBE Pspice probe window crash 752709 ALLEGRO_EDITOR PLOTTING Sheet content doesnot plots title block 752908 ALLEGRO_EDITOR INTERFACES Output from Export > DXF shows one instance of a via on the wrong layer 753226 ALLEGRO_EDITOR OTHER File > Change Editor doesn't shows the default Product Options 753622 ALLEGRO_EDITOR GRAPHICS Enahnce capture image command to default the save as location to working dir 753773 APD WIREBOND Requesting the option to set the diameter of the default WB_TACKPOINT power ring pad. 753778 APD IMPORT_DATA Import NA2 displays the design momentarily and then crashes 753866 SIG_INTEGRITY OTHER about Select by Polygon after move command 753958 CAPTURE OTHER Capture V16.3 is extremely slow while edting schematics of design placed on network drive via VPN. 754050 ALLEGRO_EDITOR UI_FORMS Why show element window disappears when scriptmode is set invisible 754143 SIP_LAYOUT OTHER SiP Package Design Integrity - running Extra Cline segments generates report without Layer number 754327 ALLEGRO_EDITOR OTHER Rename Sub Class is not working as desired. 754364 ALLEGRO_EDITOR PLACEMENT Crash when applying placement replication 754462 ALLEGRO_EDITOR SHAPE Allegro circular dynamic shape fails to fill 754819 ALLEGRO_EDITOR OTHER Create details shows wrong graphics for filled curves 755176 ALLEGRO_EDITOR PADS_IN Pads translation succeeds in v16.2 but fails in v16.3 on this ASCII file 755256 ALLEGRO_EDITOR OTHER Attached script is crashing the designs in v16.3 755610 CONCEPT_HDL CREFER Cref hyper links does not work for signals where number "0" used to define the zone for page border 755787 ALLEGRO_EDITOR EDIT_ETCH crash using resize_respace_dp command 755881 ALLEGRO_EDITOR DATABASE Swap component crashes application 756092 CAPTURE PROPERTY_EDITOR property editor flickers and loops on value edits DATE: 02-23-2010 HOTFIX VERSION: 003 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 263504 CONCEPT_HDL CHECKPLUS Checkplus fails to run if crefrpt exists in the design 726836 ALLEGRO_EDITOR SKILL axlGeo2Str() and axlGeoEqual() return different results 730820 SIP_LAYOUT PADSTACK_EDITOR Changing the Via diameter will cause the SiP tool to crash 735193 CAPTURE FONTS Pin_names and Pin_numbers get convertred into darkened blocks in ‘Zoom to all’ view in V16.2. 737307 SIG_INTEGRITY GEOMETRY_EXTRACT differential pair extraction to sigxp fails to extract coupled sparam via models 740936 ALLEGRO_EDITOR SYMBOL Confusing error message during Create Symbol 744191 ALLEGRO_EDITOR EDIT_ETCH Arc routing enhancement 744497 ALLEGRO_EDITOR INTERACTIV PCB Editor Crashes with Data Customization Feature 746572 ALLEGRO_EDITOR DATABASE Reoccuring error in attribute pointer to attribute invalid on dra. 746978 SIG_INTEGRITY SIGWAVE 2 licenses were used for SigXP and SigWave. 747219 SIP_LAYOUT SHAPE Dynamic Filleting not working with odd angles 747593 ALLEGRO_EDITOR PADS_IN Some RULE_SETS cause the PADS translation to fail. 747746 ALLEGRO_EDITOR OTHER Request for more detail in downrev.log file 748033 GRE IFP_INTERACTIVE Enhancement in GRE where Show Element on Bundleshould show the total number of nets that are part of the bundle 748333 ALLEGRO_EDITOR OTHER place by schematic page number not showing pages correctly 748375 ALLEGRO_EDITOR MANUFACT gloss - line smoothing causes crash 748818 ALLEGRO_EDITOR DRC_CONSTR Undesired DRCs shown in allegro 16.3 while moving component and the same are removed by update DRC 748865 CONSTRAINT_MGR OTHER Allegro 16.3 slow to move component with CM open 749009 APD WIREBOND a part of function of the finger alinement doesn't work 749162 SIG_EXPLORER INTERACTIV Unable to proceed after RMB > Preference > Cancel 749307 ALLEGRO_EDITOR MENTOR mbs2brd fails with error VIF_Allegro_Write 749435 CIS DESIGN_VARIANT Cannot create variant part in 16.3 749854 APD PADSTACK_EDITOR The value of user-defined mask layer is not retained in the design. 749891 ALLEGRO_EDITOR PARTITION Unable to delete existing partitions 749949 SIG_EXPLORER EXTRACTTOP A Topology extraction fails using APD and SiP series with the latest hotfix(SPB16.30.001). 750008 CAPTURE NETLIST_ALLEGRO Netlist different in SPB 16.3 and after installing SPB 16.3 hotfix 1 750591 ALLEGRO_EDITOR DATABASE Analyze diff pair object fails to display uncopled lenght values. 750888 SPECCTRA ROUTE specctra is crashing while routing 751204 F2B DESIGNVARI Design difference crashes while reading funcview 751398 ALLEGRO_EDITOR OTHER Allegro Crash when Edit is selected in Setup > Outline > Room outline 751578 ALLEGRO_EDITOR PADS_IN pads_in hangs while conversion DATE: 02-09-2010 HOTFIX VERSION: 002 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 527012 SIG_INTEGRITY IRDROP Severe Memory leak in IRDrop 623678 PCB_LIBRARIAN CORE PDV freezes when changing grid 672592 ALLEGRO_EDITOR SHAPE Shape does not void correctly untill a clearance oversize value is added 688062 PCB_LIBRARIAN CORE PDV Strange characters appear when copying text into Bus Arrows ( Text symbols) 710170 SIG_INTEGRITY IRDROP Run IR Drop even if all components on the net are not placed. 710174 SIG_INTEGRITY IRDROP Audit function for IR Drop. 726833 PSPICE DEHDL Modify the methodology for migrating 15.7 and 16.2 users of ConceptPSpice 730717 SCM UI Unable to delete a zero connection signal in SLP which has a pull-up 731017 ALLEGRO_EDITOR DRC_CONSTR DRC's show out of date when artwork is run 732145 CONCEPT_HDL OTHER Incorrectly generated VHDL netlist 740123 ALLEGRO_EDITOR GRAPHICS Capture Image command fillin missing from jrl and script files 740278 ALLEGRO_EDITOR OTHER Jumper fucntion for Single Side PCB Design 740656 ALLEGRO_EDITOR GRAPHICS Can we place custdatatips.cdt file on a site level for SPB16.3 741222 CONCEPT_HDL CORE Replace command (in Windows mode) causes crash 742389 ALLEGRO_EDITOR EDIT_ETCH Change or add message when using Countour route 743275 APD DATABASE With DRC enabled, this design seg faults in axldbid.c (solaris only). DRC update takes orders of magnitude longer on sun 743623 F2B PACKAGERXL Pxl error when using pack_ignore on reuse blocks 744348 F2B BOM PART_NAME column getting word wrapped inspite of sufficient space in the HTML BOM report. 745062 CONSTRAINT_MGR OTHER import techfile does not add new layers in cross section 745148 ALLEGRO_EDITOR GRAPHICS Allegro ptf driven HEIGHT value not pushed into 3D Viewer 745301 ALLEGRO_EDITOR DATABASE Allegro 16.3 crsh on moving component 745518 ALLEGRO_EDITOR DRC_CONSTR DRCs not shown when "Enable Antipads as Route keepout is checked in" 745745 SIP_LAYOUT WIZARDS Die Text In changing the pin names on duplicates 745785 CONSTRAINT_MGR UI_FORMS Unnecessary window opens when the cell in PCSet By layer worksheet was clicked. 746002 CONCEPT_HDL CREFER Could not find pc.db in the root design 746010 CONSTRAINT_MGR SCHEM_FTB Updating the brd file using the "Import Changes Only" option overwrites the modified constraints in 746080 CONSTRAINT_MGR OTHER Click Constraint Manager filter icons crash software 746137 APD IMPORT_DATA Import > NA2 not transalating certain layers and padstack sizes 746370 ALLEGRO_EDITOR GRAPHICS Setting infinite_cursor_bug_nt variable flips mouse movement on flip design 746519 CONCEPT_HDL CHECKPLUS CheckPlus the if statement is not seeing the True condition or the output predicate is not returning the True condition. 746546 PCB_LIBRARIAN VERIFICATION con2con choosing incorrect PART_NAME in PTF File during verification 746865 CONCEPT_HDL CORE Tool generated pspice net names in core concept design cause short with copy all. 747636 SIP_RF OTHER RFSIP Layout RF Module Export chips & connectivity is not writing die attach method to chips file DATE: 01-31-2010 HOTFIX VERSION: 001 =================================================================================================================================== CCRID PRODUCT PRODUCTLEVEL2 TITLE =================================================================================================================================== 491042 CONCEPT_HDL SECTION Prevent PackagerXL from changing visibility on SEC attribute 496910 CAPTURE NETLIST_ALLEGRO Inconsistent netlist creation 558783 PSPICE NETLISTER Why do Models with "awb*" prefix need wirte permissions to "*.ind" files? 643241 CAPTURE SCHEMATIC_EDITOR OrCAD crashed while replacing cache 654292 ALLEGRO_EDITOR DATABASE Propagation Delay constraint behaves differently between 16.01 and 16.2 662829 CONCEPT_HDL GLOBALCHANGE Global Update should honor property visibility settings in ppt_optionset 672718 SIP_LAYOUT EXPORT_DATA "Export>Symbol Spreadsheet" should export a .cvf not a .txt 676233 CAPTURE NETLIST_ALLEGRO Cross probing stops working if design name has dots 678739 CONCEPT_HDL CONSTRAINT_MGR Manually added targets in matchgroups lost when reopen CM 690618 F2B BOM Write protected template.bom fails to write callouts 700246 CIS LINK_DATABASE_PA Need option to update symbol always when linking part in CIS 705393 CONCEPT_HDL CORE ConceptHDL crashes while switching to another hierarchy level under File > Plot Preview. 708634 ALLEGRO_EDITOR SHAPE Shapes getting incorrectly displayed in 16.2 708950 CONCEPT_HDL CORE Tool crashes while trying to change the text on the schematic using a text editor. 709823 ALLEGRO_EDITOR OTHER Arcs not converted properly when upgrading symbols 713964 F2B PACKAGERXL Net property Probe_Number is getting changed during the packaging run 718119 F2B BOM Exclude the callout file name from the template.bom file 718496 SIG_INTEGRITY SIGWAVE Frequency at smith chart. 721422 CONCEPT_HDL CHECKPLUS Checkplus fails if "\\" character is used in the parameter list 721788 SCM OTHER SCM unresponsive while closing out a Block without Saving 721801 CONCEPT_HDL CORE Save As crashes DE HDL if an existing page is selected in the design 722653 F2B PACKAGERXL Packaging does not complete 725285 CONCEPT_HDL CORE nconcepthdl does not work same as concepthdl for same script. 725719 CONCEPT_HDL CORE wire pettern of Publish PDF 727062 CONCEPT_HDL CREFER Custom properties not visible for TOC symbol in schref_1 view 727194 CAPTURE CORRUPT_DESIGN Random Capture crash 727704 SCM PACKAGER ASA to PCB getting out of sync 728066 CAPTURE NETLIST_ALLEGRO Allegro PCB Edtior net cannot be generated if PACK_SHORT is used 729214 CONCEPT_HDL CORE SHOW_PNN_SIGNAME directive used with Windows Mode gives crash 730295 SIG_INTEGRITY OTHER Filled rectangle shapes not extracted properly 731183 CIS QUERY_DATABASE CIS Query fails with ODBC Error for query (Price contains 29) 732073 SIP_LAYOUT DXF_IF DXF_OUT generate an incorrect shape 732138 CONCEPT_HDL CORE Cannot change SI model assignments 732216 ADW DBEDITOR dbeditor crashes doing copy-as-new into lib folder that has partially completed chips.prt file 732249 SIG_INTEGRITY SIMULATION Probe sim with custom stimulus cause segmentation fault. Linux only. 732847 ALLEGRO_EDITOR DRC_CONSTR Manual Void uses Shape to Pin constraint to void Holes 733261 FLOWS PROJMGR Project manager does not work with the Restricted User in client server environment 733773 CONCEPT_HDL OTHER Syntax issues in DEHDL 734260 APD COLOR Why subclasses still remain visible even after global visibility is turned off. 734419 CONCEPT_HDL CORE Concept crashes in windows mode when netname is deleted on schematics generated by ASA 734555 CONSTRAINT_MGR SCHEM_FTB Import Logic does not overwrite the Constraints 735290 CONCEPT_HDL OTHER Concept's PDF Publisher has issues. 735892 CONCEPT_HDL CORE "Component Modify" changes visiblilty of Key properties 735977 ALLEGRO_EDITOR MENTOR Mentor to Allegro translation fails without any error message 736071 CONCEPT_HDL CORE Property visibility is not retained on the schematic instance when we modify the component on sch. 736165 SIP_LAYOUT SCHEMATIC_FTB about error message of "schematic to layout" 736167 CONCEPT_HDL CORE HDL crashes when I select BGA symbol in Component Browser 736911 ALLEGRO_EDITOR SHAPE No DRC displayed when Place Bounds are edge to edge 738035 ALLEGRO_EDITOR OTHER Measure function has different result between 15.7 and 16.2 version. 738129 CONSTRAINT_MGR UI_FORMS Need Diffpair Constraints option in Analysis Modes Electrical Options with Performance license 738276 ALLEGRO_EDITOR PLACEMENT No feedback in console window when placing unfound components in Allgero 16.3 738366 ALLEGRO_EDITOR GRAPHICS 3d viewer not showing some connectors with mutliple place bounds correctly 738454 SIG_INTEGRITY FIELD_SOLVERS EMS2D extracts incorrect CPW to Trace spacing 738578 ALLEGRO_EDITOR OTHER scriptmode +w doesnot work on Linux 738869 ALLEGRO_EDITOR OTHER Error msg when cds.lib contains missing SOFTINCLUDE 739116 EMI SIMULATION At EMI simulation on SigXP an extra Sigwave form is launched. 739225 ALLEGRO_EDITOR GRAPHICS Ability to lock the 'Hide Pallette' option 739599 ALLEGRO_EDITOR DRC_CONSTR drc_errchk indic 739628 ALLEGRO_EDITOR SYMBOL Opening a symbol file is crashing allegro. 739653 ALLEGRO_EDITOR SHAPE Shape created in 15.X .dra changes geometry when uprev'd to 16.X 739661 ALLEGRO_EDITOR OTHER Export netlist creates incorrect via_list syntax. 739872 ALLEGRO_EDITOR SKILL Crash while performing axlExtractToFile in 16.3 739934 SIG_INTEGRITY OTHER specctraquest crash on changing signal model 739937 MODEL_INTEGRIT PARSE zero valued estimated parasitics in ibis models 739942 ALLEGRO_EDITOR SHAPE zcopy xhatch shape creates oversize copy 740133 ALLEGRO_EDITOR DRC_CONSTR Same net DRC Update from Analysis Modes runs forever. 740281 ALLEGRO_EDITOR OTHER Jumper components where were placed in PCB disappeared 740309 SIP_LAYOUT DIE_EDITOR Moving a die pad in DIE EDITOR on G69A_U1 causes the die pads to rotate 90 degrees from the design. 740399 ALLEGRO_EDITOR COLOR Cannot automatically load custom color palette in 16.2 741210 ALLEGRO_EDITOR DATABASE Edit >Move; spin creates 'connect record not found' message 741307 ALLEGRO_EDITOR PADS_IN Shapes on some layers is not getting translated from PADS into Allegro 741313 ALLEGRO_EDITOR DRC_CONSTR Add connect slow in 16.3 741778 ALLEGRO_EDITOR COLOR Color pallete in 16.3 is not expanding when maximize dialog 741910 ALLEGRO_EDITOR PADS_IN unable to translate PADS ascii to brd 741939 ALLEGRO_EDITOR PADS_IN PADS to Allegro Translation fails or hangs. 741980 ALLEGRO_EDITOR PARTITION Import of parition does not import etch or vias. 742676 ALLEGRO_EDITOR SKILL Tpoint cannot be moved by using skill. 743161 ALLEGRO_EDITOR SCHEM_FTB Netrev crashing when importing netlist into board file. 743235 ALLEGRO_EDITOR PLACEMENT Allegro crashes when unmatching comp in placement replicate. 743243 CONSTRAINT_MGR TECHFILE Closing CM destroys tcf values when they are set to locked using fObjectNOTReadOnly 743301 SIP_LAYOUT DIE_EDITOR Edit die command creates two extra die pads 743316 CONSTRAINT_MGR DATABASE With Allegro 16.3 Constraint manager takes to long to update 743553 CONSTRAINT_MGR OTHER Net disappears if we cancel the line width edits in CM